公开(公告)号：US11676681B2

公开(公告)日：2023-06-13

申请号：US17382923

申请日：2021-07-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji Tanaka ,  Yuichiro Ishii ,  Makoto Yabuuchi

IPC: G11C11/419 ,  G11C29/50 ,  G11C5/06

CPC classification number: G11C29/50 ,  G11C5/063 ,  G11C11/419 ,  G11C2029/5004

Abstract: A semiconductor device including an SRAM capable of sensing a defective memory cell that does not satisfy desired characteristics is provided. The semiconductor device includes a memory cell, a bit line pair being coupled to the memory cell and having a voltage changed towards a power-supply voltage and a ground voltage in accordance with data of the memory cell in a read mode, and a specifying circuit for specifying a bit line out of the bit line pair. In the semiconductor device, a wiring capacitance is coupled to the bit line specified by the specifying circuit and a voltage of the specified bit line is set to a voltage between a power voltage and a ground voltage in a test mode.

公开(公告)号：US10453520B2

公开(公告)日：2019-10-22

申请号：US16013514

申请日：2018-06-20

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412

Abstract: A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.

公开(公告)号：US20180342292A1

公开(公告)日：2018-11-29

申请号：US16057113

申请日：2018-08-07

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii

IPC: G11C11/419 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

公开(公告)号：US09837140B2

公开(公告)日：2017-12-05

申请号：US15389192

申请日：2016-12-22

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C5/14 ,  G11C11/417 ,  H01L27/11 ,  H01L29/10 ,  H01L23/528

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

公开(公告)号：US09711208B2

公开(公告)日：2017-07-18

申请号：US14878049

申请日：2015-10-08

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato Yokoyama ,  Yuichiro Ishii

IPC: G11C11/417 ,  G11C5/14

CPC classification number: G11C11/418 ,  G11C5/148 ,  G11C11/417

Abstract: There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode.

公开(公告)号：US09685225B2

公开(公告)日：2017-06-20

申请号：US15232216

申请日：2016-08-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuichiro Ishii

IPC: G11C5/14 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412 ,  G11C7/20

CPC classification number: G11C11/418 ,  G11C5/147 ,  G11C7/20 ,  G11C11/412 ,  G11C11/419

Abstract: The disclosed invention provides a semiconductor storage device that creates no trouble, independently of power-on sequence. A semiconductor storage device includes a first power supply for the memory cells, a second power supply which is turned on independently of the first power supply and provided for a peripheral circuit which is electrically coupled to the memory cells, and a word line level fixing circuit for fixing the level of the word lines, which operates in accordance with turn-on of the first power supply. The word line level fixing circuit includes multiple level fixing transistors which are provided to correspond respectively to the word lines and provided between one of the word lines and a fixed potential and a level fixing control circuit which controls the level fixing transistors in accordance with input of a signal responding to turn-on of the second power supply.

公开(公告)号：US20160071578A1

公开(公告)日：2016-03-10

申请号：US14942861

申请日：2015-11-16

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C7/12 ,  G11C2207/2227

Abstract: A semiconductor storage device includes an SRAM memory cell composed of a drive transistor, a transfer transistor and a load transistor, an I/O circuit that is connected to bit lines connected to the memory cell, and an operating mode control circuit that switches an operating mode of the I/O circuit between a resume standby mode and a normal operation mode, wherein the I/O circuit includes a write driver that writes data to bit lines, a sense amplifier that reads data from the bit lines, a first switch inserted between the bit lines and the write driver, a second switch inserted between the bit lines and the sense amplifier, a precharge circuit that precharges the bit lines, and a control circuit that controls the first and second switches and the precharge circuit according to a signal from the operating mode control circuit.

公开(公告)号：US10658028B2

公开(公告)日：2020-05-19

申请号：US16062571

申请日：2016-11-14

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Shinji Tanaka

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/06 ,  G11C8/14 ,  G11C11/418 ,  H01L27/11 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C7/02

Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.

公开(公告)号：US10515672B2

公开(公告)日：2019-12-24

申请号：US16229776

申请日：2018-12-21

Applicant: Renesas Electronics Corporation

Inventor： Shinji Tanaka ,  Yuichiro Ishii ,  Masaki Tsukude ,  Yoshikazu Saito

IPC: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/12 ,  G11C29/04 ,  G11C29/18 ,  G11C29/50 ,  G11C29/28

Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

公开(公告)号：US10453519B2

公开(公告)日：2019-10-22

申请号：US16143940

申请日：2018-09-27

Applicant: Renesas Electronics Corporation

Inventor： Yohei Sawada ,  Makoto Yabuuchi ,  Yuichiro Ishii

IPC: G11C11/417 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C5/14

Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.