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    Semiconductor device including a content reference memory
    1.
    发明授权
    Semiconductor device including a content reference memory 有权

    公开(公告)号：US11551755B2

    公开(公告)日：2023-01-10

    申请号：US17318632

    申请日：2021-05-12

    申请人： RENESAS ELECTRONICS CORPORATION

    发明人： Makoto Yabuuchi

    IPC分类号： G11C15/00 ,  G11C15/04 ,  G11C8/08 ,  G11C7/12 ,  G11C7/06

    摘要： A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

    Content addressable memory
    2.
    发明授权
    Content addressable memory 有权

    公开(公告)号：US10705143B2

    公开(公告)日：2020-07-07

    申请号：US15916016

    申请日：2018-03-08

    申请人： Renesas Electronics Corporation

    发明人： Makoto Yabuuchi ,  Shinji Tanaka

    IPC分类号： G01R31/00 ,  G01R31/3177 ,  G11C15/04 ,  G06F11/27 ,  G06F11/00 ,  G11C29/12

    摘要： An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

    Ternary content addressable memory wiring arrangement
    3.
    发明授权
    Ternary content addressable memory wiring arrangement 有权

    公开(公告)号：US10541028B2

    公开(公告)日：2020-01-21

    申请号：US16030136

    申请日：2018-07-09

    申请人： RENESAS ELECTRONICS CORPORATION

    发明人： Makoto Yabuuchi

    IPC分类号： G11C15/04 ,  H01L23/528 ,  H01L23/552 ,  H01L27/088 ,  H01L27/105 ,  G11C8/08

    摘要： A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10453519B2

    公开(公告)日：2019-10-22

    申请号：US16143940

    申请日：2018-09-27

    申请人： Renesas Electronics Corporation

    发明人： Yohei Sawada ,  Makoto Yabuuchi ,  Yuichiro Ishii

    IPC分类号： G11C11/417 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C5/14

    摘要： A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.

    Semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US10304527B2

    公开(公告)日：2019-05-28

    申请号：US15919525

    申请日：2018-03-13

    申请人： Renesas Electronics Corporation

    发明人： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC分类号： G11C17/12 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    摘要： There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Semiconductor memory device for stably reading and writing data
    7.
    发明授权
    Semiconductor memory device for stably reading and writing data 有权

    公开(公告)号：US10262707B2

    公开(公告)日：2019-04-16

    申请号：US15586870

    申请日：2017-05-04

    申请人： Renesas Electronics Corporation

    发明人： Koji Nii ,  Shigeki Ohbayashi ,  Yasumasa Tsukamoto ,  Makoto Yabuuchi

    IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C5/06 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419

    摘要： In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

    Semiconductor storage device
    8.
    发明授权
    Semiconductor storage device 有权

    公开(公告)号：US10049723B2

    公开(公告)日：2018-08-14

    申请号：US15606903

    申请日：2017-05-26

    申请人： Renesas Electronics Corporation

    发明人： Makoto Yabuuchi ,  Shinji Tanaka

    IPC分类号： G11C11/00 ,  G11C11/417

    摘要： A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

    Semiconductor storage device and test method thereof using a common bit line
    10.
    发明授权
    Semiconductor storage device and test method thereof using a common bit line 有权
    半导体存储器件及其使用公共位线的测试方法

    公开(公告)号：US09508419B2

    公开(公告)日：2016-11-29

    申请号：US14454357

    申请日：2014-08-07

    申请人： Renesas Electronics Corporation

    发明人： Makoto Yabuuchi

    IPC分类号： G11C16/10 ,  G11C11/412 ,  G11C7/14 ,  G11C29/12 ,  G11C11/419 ,  H01L27/11

    CPC分类号： G11C29/1201 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/1104 ,  H01L27/1116

    摘要： Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.

    摘要翻译： 提供一种半导体存储装置，包括：第一存储单元; 第一个字线 第一位线 第一个通用位线; 第二存储单元; 第二个字线 第二位线 第二个通用位线; 第一选择电路，其将第一公共位线连接到从第一位线选择的第一位线; 第二选择电路，其将所述第二公共位线连接到从所述第二位线选择的第二位线; 字线驱动器，其激活第一和第二字线中的任何一个; 参考电流供应单元，其将第一和第二公共位线之间的公共位线提供参考电流，所述公共位线未电连接到数据读取目标存储器单元; 以及放大第一和第二公共位线之间的电位差的读出放大器。