公开(公告)号：US10705143B2

公开(公告)日：2020-07-07

申请号：US15916016

申请日：2018-03-08

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Shinji Tanaka

IPC: G01R31/00 ,  G01R31/3177 ,  G11C15/04 ,  G06F11/27 ,  G06F11/00 ,  G11C29/12

Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.

公开(公告)号：US10658028B2

公开(公告)日：2020-05-19

申请号：US16062571

申请日：2016-11-14

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Shinji Tanaka

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/06 ,  G11C8/14 ,  G11C11/418 ,  H01L27/11 ,  G11C5/14 ,  G11C7/12 ,  G11C8/08 ,  G11C7/02

Abstract: A semiconductor storage device includes a plurality of memory cells arranged in a matrix, a word line provided corresponding to a memory cell row, a dummy word line formed in a metal interconnection layer adjacent to a metal interconnection layer in which the word line is formed, a word driver circuit configured to drive the word line, and a dummy word driver circuit configured to increase voltage on the word line based on interline capacitance between the word line and the dummy word line.

公开(公告)号：US10515672B2

公开(公告)日：2019-12-24

申请号：US16229776

申请日：2018-12-21

Applicant: Renesas Electronics Corporation

Inventor： Shinji Tanaka ,  Yuichiro Ishii ,  Masaki Tsukude ,  Yoshikazu Saito

IPC: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/12 ,  G11C29/04 ,  G11C29/18 ,  G11C29/50 ,  G11C29/28

Abstract: A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

公开(公告)号：US10049723B2

公开(公告)日：2018-08-14

申请号：US15606903

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Shinji Tanaka

IPC: G11C11/00 ,  G11C11/417

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided.The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal. Setting and cancelling of the second low power consumption mode, in which regions where a power source is shut down are different from those in the first low power consumption mode, of each memory module are sequentially performed according to the first control signal that is propagated through the propagation path.

公开(公告)号：US09972401B2

公开(公告)日：2018-05-15

申请号：US15606562

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Shunya Nagata ,  Shinji Tanaka

IPC: G11C8/00 ,  G11C29/12 ,  G11C7/10 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412 ,  G11C29/02 ,  G11C29/18

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US10964404B2

公开(公告)日：2021-03-30

申请号：US16540788

申请日：2019-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato Yokoyama ,  Shinji Tanaka

IPC: G11C7/00 ,  G11C29/18 ,  G11C7/22 ,  G11C29/12 ,  G11C29/26

Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

公开(公告)号：US10002662B2

公开(公告)日：2018-06-19

申请号：US15716639

申请日：2017-09-27

Applicant: Renesas Electronics Corporation

Inventor： Shinji Tanaka ,  Makoto Yabuuchi ,  Yuta Yoshida

IPC: G11C5/06 ,  G11C11/419 ,  G11C11/418 ,  G11C7/22 ,  G11C7/08 ,  G11C11/415 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

公开(公告)号：US09805821B2

公开(公告)日：2017-10-31

申请号：US15234910

申请日：2016-08-11

Applicant: Renesas Electronics Corporation

Inventor： Shinji Tanaka ,  Yuichiro Ishii ,  Masaki Tsukude ,  Yoshikazu Saito

IPC: G11C29/02 ,  G11C11/418 ,  G11C11/419 ,  G11C29/12 ,  G11C29/04 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

公开(公告)号：US09548106B2

公开(公告)日：2017-01-17

申请号：US15134981

申请日：2016-04-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。

公开(公告)号：US09214222B2

公开(公告)日：2015-12-15

申请号：US14504994

申请日：2014-10-02

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Yoshikazu Saito ,  Shinji Tanaka ,  Koji Nii

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/22 ,  G11C15/00 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  G11C15/04

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。