公开(公告)号：US20170092378A1

公开(公告)日：2017-03-30

申请号：US15234910

申请日：2016-08-11

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Yuichiro ISHll ,  Masaki TSUKUDE ,  Yoshikazu SAITO

IPC: G11C29/12 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C7/00 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/12005 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/18 ,  G11C29/28 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

公开(公告)号：US20160125932A1

公开(公告)日：2016-05-05

申请号：US14878049

申请日：2015-10-08

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato YOKOYAMA ,  Yuichiro ISHll

IPC: G11C11/417

CPC classification number: G11C11/418 ,  G11C5/148 ,  G11C11/417

Abstract: There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode.

Abstract translation: 提供了一种半导体存储装置，其中存储器单元可以容易地在待机模式下被设置在适当的电位，以及用于控制存储器单元的源极线的电位的电路的面积的减小。 半导体存储装置包括静态型存储单元和控制电路。 控制电路包括：第一开关晶体管，设置在与驱动晶体管的源电极耦合的源极线与第一电压之间;第二开关晶体管，与第一开关晶体管并联;以及源极线电位控制电路， 第一和第二开关晶体管导通，以在存储器单元工作时将源极线耦合到第一电压，并且将第一开关晶体管设置为不导通，并将耦合到源极线的第二开关晶体管的栅电极设置为待机模式 。