知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.014 seconds)

    SEMICONDUCTOR MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20160092293A1

    公开(公告)日：2016-03-31

    申请号：US14868238

    申请日：2015-09-28

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    Abstract translation: 本发明提供一种可以通过具有低面积开销的简单方法执行地址解码器的故障检测的半导体存储器件。 半导体存储器件包括：具有以矩阵排列的多个第一存储单元的第一存储器阵列; 与每个存储单元行对应地提供的多个字线; 地址解码器，用于根据输入的地址信息从字线中选择字线; 在列方向上与第一存储器阵列相邻设置的第二存储器阵列，具有多个第二存储单元，能够读取在先前存储的字线的选择中使用的地址信息，根据扩展的字线的选择 到第二存储器阵列; 以及比较电路，用于将输入地址信息与从第二存储器阵列读取的地址信息进行比较。

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180018211A1

    公开(公告)日：2018-01-18

    申请号：US15710803

    申请日：2017-09-20

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170103803A1

    公开(公告)日：2017-04-13

    申请号：US15389192

    申请日：2016-12-22

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Kazumasa YANAGISAWA

    IPC: G11C11/417 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

    Semiconductor Device, Test Program, and Test Method
    6.
    发明申请
    Semiconductor Device, Test Program, and Test Method 有权
    半导体器件，测试程序和测试方法

    公开(公告)号：US20160254062A1

    公开(公告)日：2016-09-01

    申请号：US15000027

    申请日：2016-01-18

    Applicant: Renesas Electronics Corporation

    Inventor： Atsushi MIYANISHI ,  Yuichiro ISHII ,  Yoshisato YOKOYAMA

    IPC: G11C29/04 ,  G11C11/417

    CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

    Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed.An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

    Abstract translation: 当进行常温下的筛选试验而不是SRAM的低温筛选试验时，过度杀虫剂被降低，并且由于局部变化而导致的缺陷流出的风险被抑制。 包括字线，位线对，存储单元和驱动位线对的驱动电路的SRAM具有能够将位线对的一个位线驱动为高电平（VDD）电位的功能 并在将数据写入存储单元时将其他位线驱动为比正常写入的低电平（VSS）电位稍高的中间电位（VSS +几十mV至几十mV）。

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190034260A1

    公开(公告)日：2019-01-31

    申请号：US16152052

    申请日：2018-10-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yuichiro ISHII ,  Atsushi MIYANISHI ,  Yoshikazu SAITO

    IPC: G06F11/07

    CPC classification number: G06F11/0751 ,  G06F11/073

    Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160126953A1

    公开(公告)日：2016-05-05

    申请号：US14866544

    申请日：2015-09-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro Ishii ,  Atsushi MIYANISHI ,  Kazumasa YANAGISAWA

    IPC: H03K19/00 ,  H03K17/687

    CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

    Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

    Abstract translation: 一种半导体器件包括接受主动模式下的电力供给的第一电源线，接受主动模式和备用模式的电力供给的第二电源线，与第一和第二电力线耦合的存储电路， 第二电源线和第一开关，其将第一电源线与第二电源线以活动模式电耦合，并且在待机模式下将第一电源线与第二电源线电耦合。 存储器电路包括存储器阵列，外围电路和第二开关。 第一和第二开关中的每一个包括第一PMOS晶体管和第二PMOS晶体管。

Patent Agency Ranking