公开(公告)号：US20220199153A1

公开(公告)日：2022-06-23

申请号：US17548989

申请日：2021-12-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunya NAGATA

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: The control circuit of the semiconductor device initializes a plurality of memory cells. The method is that when the reset signal is at a high level, the control circuit turns off the first transistor, selects multiple word lines, turns off the precharge circuit, turns on the write column switch, and turns off the read column switch. Then, the control circuit initializes a plurality of memory cells by setting the first bit line to the low level and the second bit line to the high level by the writing circuit.

公开(公告)号：US20180226135A1

公开(公告)日：2018-08-09

申请号：US15947075

申请日：2018-04-06

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C11/418 ,  G11C29/18 ,  G11C29/02 ,  G11C11/419 ,  G11C7/10 ,  G11C11/412 ,  G11C11/406 ,  G11C8/16 ,  G11C8/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20170263333A1

公开(公告)日：2017-09-14

申请号：US15606562

申请日：2017-05-26

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20200328732A1

公开(公告)日：2020-10-15

申请号：US16828582

申请日：2020-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi TASAKI ,  Shunya NAGATA

IPC: H03K3/037 ,  H03K19/20 ,  H03K5/14

Abstract: A semiconductor device includes: a plurality of P-channel type MOS transistors each whose source-drain path being coupled between a first wiring to which a power supply potential is to be supplied and a power supply node included in a logic circuit block, and a plurality of N-channel type MOS transistors each whose source-drain path being coupled between a ground node included in the logic circuit block and a second wiring to which a ground potential is to be supplied. Also, during standby state, each of the plurality of P-channel type MOS transistors and the plurality of N-channel type MOS transistors is diode-connected. According to the above semiconductor device, the current consumption of a logic circuit included in the logic circuit block during standby state can be reduced, and the logic circuit can be returned from standby state to normal operation state in a short time.

公开(公告)号：US20180349222A1

公开(公告)日：2018-12-06

申请号：US15984572

申请日：2018-05-21

Applicant: Renesas Electronics Corporation

Inventor： Takeshi HASHIZUME ,  Naoya FUJITA ,  Shunya NAGATA ,  Yoshisato YOKOYAMA ,  Katsumi SHINBO ,  Kouji SATOU

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G11C5/04 ,  G11C11/413 ,  G11C29/52 ,  G11C2029/0411

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

公开(公告)号：US20230088709A1

公开(公告)日：2023-03-23

申请号：US17879524

申请日：2022-08-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kouji SATOU ,  Shunya NAGATA ,  Jiro ISHIKAWA

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

公开(公告)号：US20170352399A1

公开(公告)日：2017-12-07

申请号：US15613882

申请日：2017-06-05

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato YOKOYAMA ,  Yoshikazu SAITO ,  Shunya NAGATA ,  Toshiaki SANO ,  Takeshi HASHIZUME

IPC: G11C11/405 ,  G11C8/16 ,  G11C7/06 ,  G11C11/406 ,  H03K19/177 ,  G11C11/408

CPC classification number: G11C11/405 ,  G11C7/062 ,  G11C8/16 ,  G11C11/40603 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/32 ,  G11C2029/1202 ,  G11C2207/104 ,  H03K19/1776

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

公开(公告)号：US20170117060A1

公开(公告)日：2017-04-27

申请号：US15281947

申请日：2016-09-30

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki SANO ,  Shunya NAGATA ,  Shinji TANAKA

IPC: G11C29/12 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C29/12 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C29/025 ,  G11C29/12015 ,  G11C29/18 ,  G11C2029/1202

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

公开(公告)号：US20250078946A1

公开(公告)日：2025-03-06

申请号：US18806844

申请日：2024-08-16

Applicant: Renesas Electronics Corporation

Inventor： Tomohiro MIURA ,  Kouji SATOU ,  Shunya NAGATA

IPC: G11C29/12 ,  G11C29/42

Abstract: Providing a memory device that initializes memory cell data in a batch by specifying initialization data, or a memory device that initializes memory cell data in a batch by partially masking the initialization area. A memory device is provided that includes a control circuit that receives an initialization mode signal transmitted from an initialization control circuit and generates an internal clock and a write control signal, an IO (Input/Output) input circuit that applies a Low level to the True side or Bar side of a bit line according to initialization data transmitted from the initialization control circuit, and a selection circuit that simultaneously selects multiple word lines and multiple bit lines, and writes the initialization data simultaneously into a memory cell connected to the selected word lines and bit lines.

公开(公告)号：US20230207034A1

公开(公告)日：2023-06-29

申请号：US18062262

申请日：2022-12-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunya NAGATA ,  Jun MATSUSHIMA

IPC: G11C29/12 ,  G11C11/418

CPC classification number: G11C29/12005 ,  G11C11/418 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.