公开(公告)号：US20230088709A1

公开(公告)日：2023-03-23

申请号：US17879524

申请日：2022-08-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kouji SATOU ,  Shunya NAGATA ,  Jiro ISHIKAWA

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.