公开(公告)号：US20170089979A1

公开(公告)日：2017-03-30

申请号：US15220427

申请日：2016-07-27

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki IWATA ,  Jun MATSUSHIMA

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/31813 ,  G01R31/3183 ,  G01R31/318536 ,  G01R31/318583

Abstract: It is possible to reduce the number of test point circuits to be inserted necessary to accomplish a target fault coverage, to suppress an increase in an area overhead, and to reduce a test time. A test point circuit according to an embodiment constitutes a scan chain, and captures, in one capture operation period of a clock sequential test, a first operation result in a second capture clock that comes after a first capture clock, the first operation result having been captured by a test point circuit at a previous stage or a last stage of the scan chain in the first capture clock.

公开(公告)号：US20250053191A1

公开(公告)日：2025-02-13

申请号：US18795290

申请日：2024-08-06

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Jun MATSUSHIMA

IPC: G06F1/12

Abstract: The technology provided enables the acceleration of the clock. The semiconductor device comprises a counter circuit configured to generate a read signal when the count number reaches a predetermined number, a buffer configured to store test data and sequentially output the test data in the order stored when the read signal indicates a valid value, and a first scan test circuit that sequentially captures the test data output from the buffer.

公开(公告)号：US20180277237A1

公开(公告)日：2018-09-27

申请号：US15862041

申请日：2018-01-04

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Hideshi MAENO ,  Jun MATSUSHIMA

IPC: G11C29/42 ,  G11C29/18 ,  G06F3/06

CPC classification number: G11C29/42 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0688 ,  G11C29/18 ,  G11C29/20 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/2602 ,  G11C2029/3202 ,  G11C2029/4402

Abstract: An address generation circuit generates a target address to be tested in a memory. A test data generation circuit generates write data for the address and expected value data for read data from the address. A judgment circuit compares matching/non-matching of the read data and the expected value data, for each address, judges that error correction is possible when the number of non-matching bits is within a range of numbers of bits to be error-corrected by an ECC circuit, and judges that error correction is not possible when the number is not within the range.

公开(公告)号：US20230207034A1

公开(公告)日：2023-06-29

申请号：US18062262

申请日：2022-12-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunya NAGATA ,  Jun MATSUSHIMA

IPC: G11C29/12 ,  G11C11/418

CPC classification number: G11C29/12005 ,  G11C11/418 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: In an SRAM circuit mounted in a semiconductor device, power supply voltage reduction circuits generate reduction voltage obtained by reducing an external power supply voltage. A first power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a drive voltage supplied to a word line driver. A second power supply voltage selection circuit selects one of the external power supply voltage and the reduction voltage as a voltage of a power supply line supplying an operating voltage to a memory cell.

公开(公告)号：US20200072903A1

公开(公告)日：2020-03-05

申请号：US16534560

申请日：2019-08-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshinori NISHIDA ,  Yoichi MAEDA ,  Jun MATSUSHIMA

IPC: G01R31/3185 ,  G01R31/3181 ,  G01R31/3183 ,  G01R31/3187

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

公开(公告)号：US20180090225A1

公开(公告)日：2018-03-29

申请号：US15658734

申请日：2017-07-25

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Hideshi MAENO ,  Jun MATSUSHIMA

IPC: G11C29/52 ,  G06F11/27

CPC classification number: G11C29/52 ,  G06F11/27 ,  G11C29/36 ,  G11C29/38 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

公开(公告)号：US20180059183A1

公开(公告)日：2018-03-01

申请号：US15549624

申请日：2015-04-16

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Jun MATSUSHIMA ,  Hiroki WADA

IPC: G01R31/319 ,  G01R31/3185 ,  G01R31/3193 ,  G06F11/267

CPC classification number: G01R31/31921 ,  G01R31/318508 ,  G01R31/318516 ,  G01R31/318547 ,  G01R31/318594 ,  G01R31/31922 ,  G01R31/3193 ,  G06F11/267

Abstract: A semiconductor device includes a FIFO, a test data write circuit that sequentially writes a plurality of test data to the FIFO in synchronization with a first clock signal, and a test control circuit that, in parallel with writing of the plurality of test data to the FIFO by the test data write circuit, sequentially reads a plurality of test data stored in the FIFO in synchronization with a second clock signal that is not synchronous with the first clock signal and performs a scan test of a circuit to be tested.

公开(公告)号：US20170343607A1

公开(公告)日：2017-11-30

申请号：US15493311

申请日：2017-04-21

Applicant: Renesas Electronics Corporation

Inventor： Yoichi MAEDA ,  Jun MATSUSHIMA

IPC: G01R31/3185 ,  G01R31/26

CPC classification number: G01R31/318525 ,  G01R31/2601 ,  G01R31/318547

Abstract: In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.