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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230088709A1

    公开(公告)日：2023-03-23

    申请号：US17879524

    申请日：2022-08-02

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kouji SATOU ,  Shunya NAGATA ,  Jiro ISHIKAWA

    IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

    Abstract: A semiconductor device includes a first regulator for generating a first power supply potential, a second regulator for generating a second power supply potential lower than the first power supply potential, and a static random access memory (SRAM) having a normal operation mode and a resume standby mode. The SRAM includes power supply switching circuits receiving a first power supply potential and a second power supply potential, and a memory array including a plurality of memory cells. When the SRAM is in the normal operation mode, the power switch circuit is controlled so that the first power supply potential is supplied from the power switch circuit to the memory array, and when SRAM is in the resume standby mode, the second power supply potential is supplied from the power switch circuit to the memory array.

    MEMORY DEVICE
    2.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20250078946A1

    公开(公告)日：2025-03-06

    申请号：US18806844

    申请日：2024-08-16

    Applicant: Renesas Electronics Corporation

    Inventor： Tomohiro MIURA ,  Kouji SATOU ,  Shunya NAGATA

    IPC: G11C29/12 ,  G11C29/42

    Abstract: Providing a memory device that initializes memory cell data in a batch by specifying initialization data, or a memory device that initializes memory cell data in a batch by partially masking the initialization area. A memory device is provided that includes a control circuit that receives an initialization mode signal transmitted from an initialization control circuit and generates an internal clock and a write control signal, an IO (Input/Output) input circuit that applies a Low level to the True side or Bar side of a bit line according to initialization data transmitted from the initialization control circuit, and a selection circuit that simultaneously selects multiple word lines and multiple bit lines, and writes the initialization data simultaneously into a memory cell connected to the selected word lines and bit lines.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230186981A1

    公开(公告)日：2023-06-15

    申请号：US17993364

    申请日：2022-11-23

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shunya NAGATA ,  Kouji SATOU

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/418

    Abstract: Provided is a technology capable of initializing data in memory cells at a relatively high speed while suppressing an area increase. Based on a fact that the reset signal is turned to a high level, a control circuit of a semiconductor device turns a first transistor to an OFF state, a plurality of word lines to a selection state, a precharge circuit to the OFF state, column switches for writing to an ON state, and column switches for reading to the OFF state, causes write circuits to turn first bit lines and second bit lines to a low level and a high level, respectively, and initializes a plurality of memory cells.

    SEMICONDUCTOR CHIP
    4.
    发明公开
    SEMICONDUCTOR CHIP 审中-公开

    公开(公告)号：US20240170054A1

    公开(公告)日：2024-05-23

    申请号：US18513124

    申请日：2023-11-17

    Applicant: Renesas Electronics Corporation

    Inventor： Daiki KITAGATA ,  Kouji SATOU ,  Toshiaki SANO

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: A plurality of SRAM macros each including a memory cell array, an input/output circuit, a word line driver, and a control circuit are mounted on a semiconductor chip. Each of the SRAM macros includes a determination block disposed in the control circuit and configured to generate a mode signal for determining a read assist amount and a write assist amount based on a power supply voltage of the SRAM macro, and an assist circuit that performs a read assist operation and a write assist operation based on the mode signal generated by the determination block.

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