公开(公告)号：US20180349222A1

公开(公告)日：2018-12-06

申请号：US15984572

申请日：2018-05-21

Applicant: Renesas Electronics Corporation

Inventor： Takeshi HASHIZUME ,  Naoya FUJITA ,  Shunya NAGATA ,  Yoshisato YOKOYAMA ,  Katsumi SHINBO ,  Kouji SATOU

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G11C5/04 ,  G11C11/413 ,  G11C29/52 ,  G11C2029/0411

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.