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    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190189197A1

    公开(公告)日：2019-06-20

    申请号：US16176299

    申请日：2018-10-31

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Yuichiro ISHII ,  Yohei SAWADA ,  Makoto YABUUCHI

    IPC: G11C11/419 ,  G11C11/412

    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权
    半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗

    公开(公告)号：US20140126278A1

    公开(公告)日：2014-05-08

    申请号：US14151581

    申请日：2014-01-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING TIMING CONTROL FOR READ-WRITE MEMORY ACCESS OPERATIONS 有权
    具有读写存取存取操作的时序控制的半导体器件

    公开(公告)号：US20130194882A1

    公开(公告)日：2013-08-01

    申请号：US13750328

    申请日：2013-01-25

    Applicant: Renesas Electronics Corporation

    Inventor： Yuichiro ISHII ,  Yoshikazu SAITO ,  Shinji TANAKA ,  Koji NII

    IPC: G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412 ,  G11C15/00 ,  G11C15/04

    Abstract: A semiconductor device avoids the disturb problem and the collision between write and read operations in a DP-SRAM cell or a 2P-SRAM cell. The semiconductor device 1 includes a write word line WLA and a read word line WLB each coupled to memory cells 3. A read operation activates the read word line WLB corresponding to the selected memory cell 3. A write operation activates the write word line WLA corresponding to the selected memory cell 3. The selected write word line WLA is activated after activation of the selected read word line WLB in an operation cycle that performs both read and write operations.

    Abstract translation: 半导体器件避免了干扰问题以及DP-SRAM单元或2P-SRAM单元中的写入和读取操作之间的冲突。 半导体器件1包括写入字线WLA和读取字线WLB，每个读取字线WLB都耦合到存储器单元3.读取操作激活对应于所选择的存储器单元3的读取字线WLB。写入操作激活相应的写入字线WLA 所选择的写入字线WLA在执行读取和写入操作的操作周期中激活所选择的读取字线WLB之后被激活。

    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA 审中-公开

    公开(公告)号：US20170236579A1

    公开(公告)日：2017-08-17

    申请号：US15586870

    申请日：2017-05-04

    Applicant: Renesas Electronics Corporation

    Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/417

    Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20170047332A1

    公开(公告)日：2017-02-16

    申请号：US15338390

    申请日：2016-10-30

    Applicant: Renesas Electronics Corporation

    Inventor： Koji NII

    IPC: H01L27/11 ,  H01L23/528 ,  H01L29/78 ,  H01L27/02 ,  G11C11/412 ,  G11C11/417 ,  H01L29/10 ,  H01L29/417

    CPC classification number: H01L27/1104 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1116 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential write and readout port, and the 2 port may serve as a single ended readout dedicated port. While the occupied area of an embedded SRAM can be reduced, the number of write and readout ports is limited to only one, and readout characteristics as fast as differential readout cannot be expected in single ended readout. A new arrangement is therefore provided in which three differential write and readout ports are included in a memory cell structure of the embedded SRAM, an N-well region, for example, is arranged at the center of a cell, and a P-well region is arranged on both sides thereof.

    Abstract translation: 在图像信息芯片等中，多端口SRAM嵌有逻辑电路。 当使用3端口时，1端口可以用作差分写入和读出端口，并且2端口可以用作单端读出专用端口。 虽然可以减少嵌入式SRAM的占用面积，但是写入和读出端口的数量仅限于一个，并且在单端读出中不能期望读出特性与差分读出一样快。 因此，提供了一种新的布置，其中三个差分写入和读出端口包括在嵌入式SRAM的存储单元结构中，例如N阱区域布置在单元的中心，并且P阱区域 布置在其两侧。

    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION
    9.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION 有权
    具有生成芯片识别信息能力的半导体器件

    公开(公告)号：US20160358667A1

    公开(公告)日：2016-12-08

    申请号：US15240863

    申请日：2016-08-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

    IPC: G11C29/12 ,  G11C11/417

    CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

    Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

    Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏;测试地址存储单元，被配置为存储测试地址; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION
    10.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION 有权
    具有生成芯片识别信息能力的半导体器件

    公开(公告)号：US20140070212A1

    公开(公告)日：2014-03-13

    申请号：US14022721

    申请日：2013-09-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

    IPC: G06K19/07

    CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

    Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

    Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏; 被配置为存储测试地址的测试地址存储单元; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

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