公开(公告)号：US20190027212A1

公开(公告)日：2019-01-24

申请号：US16143940

申请日：2018-09-27

Applicant: Renesas Electronics Corporation

Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

IPC: G11C11/417 ,  G11C11/413 ,  G11C11/412 ,  G11C11/41 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.

公开(公告)号：US20220028455A1

公开(公告)日：2022-01-27

申请号：US17382322

申请日：2021-07-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yohei SAWADA ,  Masao MORIMOTO ,  Makoto YABUUCHI

IPC: G11C15/04

Abstract: The plurality of CAM cells MC are configured to discriminate a match or mismatch between stored data stored in advance and search data. A match line is coupled to a plurality of CAM cells, and has a voltage level controlled based on discrimination results of the plurality of CAM cells. A first transistor and a second transistor are coupled in series between a common match output line and a predetermined power source. The first transistor is controlled to be turned ON or OFF based on a voltage level of the match line, and the second transistor is controlled to be turned ON or OFF by a search enabling signal asserted at the time of a search operation.

公开(公告)号：US20190189197A1

公开(公告)日：2019-06-20

申请号：US16176299

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Yuichiro ISHII ,  Yohei SAWADA ,  Makoto YABUUCHI

IPC: G11C11/419 ,  G11C11/412

Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

公开(公告)号：US20220165332A1

公开(公告)日：2022-05-26

申请号：US17520020

申请日：2021-11-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yohei SAWADA

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/11

Abstract: A semiconductor device includes a main circuit and a peripheral circuit inputting/outputting a signal from/to the main circuit, the main circuit including: a memory cell array; a sense amplifier; a first output holding circuit holding the read data output from the sense amplifier; a second output holding circuit receiving the read data as its input output from the first output holding circuit; and a delay circuit outputting a delay signal for activating the second output holding circuit to be later than the first output holding circuit. The delay circuit includes an element applying a load capacitance to a wiring of the delay signal. A power-supply voltage being a first voltage is supplied to the memory cell array, the sense amplifier and the first output holding circuit. A power-supply voltage being a second voltage is supplied to the delay circuit, the second output holding circuit and the peripheral circuit.

公开(公告)号：US20170309326A1

公开(公告)日：2017-10-26

申请号：US15513138

申请日：2015-03-31

Applicant: Renesas Electronics Corporation

Inventor： Yohei SAWADA ,  Makoto YABUUCHI ,  Yuichiro ISHII

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/148 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413

Abstract: A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground interconnection commonly connected to each of the memory cells; and a first potential control circuit for controlling a potential of the ground interconnection depending on an operation mode. The first potential control circuit includes a first NMOS transistor and a first PMOS transistor connected in parallel to each other between a around node providing a ground potential and the ground interconnection.

公开(公告)号：US20230253042A1

公开(公告)日：2023-08-10

申请号：US18163590

申请日：2023-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji TANAKA ,  Yohei SAWADA ,  Masao MORIMOTO

IPC: G11C15/04 ,  G11C5/14

CPC classification number: G11C15/04 ,  G11C5/148

Abstract: A semiconductor device includes a memory array having a plurality of associative memory cells arranged in a matrix form for storing entries. The memory array is divided into a plurality of memory blocks for sequentially performing a retrieval operation along a column direction, and further includes a plurality of match lines corresponding to the respective memory blocks and provided correspondingly to each memory cell row, a plurality of search lines corresponding to the respective memory blocks and provided correspondingly to each memory cell column, and a plurality of match amplifiers corresponding to the respective memory blocks and provided to the plurality of match lines. The match line provided correspondingly to the preceding memory block is set to become shorter than the match line provided correspondingly to the subsequent memory block. The memory array further includes a timing control unit for controlling timing for driving the search line of the subsequent memory block based on a length of the match line provided correspondingly to the preceding memory block.