公开(公告)号：US20140126278A1

公开(公告)日：2014-05-08

申请号：US14151581

申请日：2014-01-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20160155825A1

公开(公告)日：2016-06-02

申请号：US15017459

申请日：2016-02-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshiaki IWAMATSU ,  Takashi TERADA ,  Hirofumi SHINOHARA ,  Kozo ISHIKAWA ,  Ryuta TSUCHIYA ,  Kiyoshi HAYASHI

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/308 ,  H01L21/321

CPC classification number: H01L29/66795 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/321 ,  H01L29/785

Abstract: An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.

公开(公告)号：US20160005765A1

公开(公告)日：2016-01-07

申请号：US14855150

申请日：2015-09-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/78 ,  H01L29/06 ,  H01L29/36

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

公开(公告)号：US20150061006A1

公开(公告)日：2015-03-05

申请号：US14459999

申请日：2014-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi SHINOHARA ,  Hidekazu ODA ,  Toshiaki IWAMATSU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/26586 ,  H01L21/76229 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/36 ,  H01L29/45 ,  H01L29/66598 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7824 ,  H01L29/7835

Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.

Abstract translation: 在具有通过绝缘层形成在半导体衬底上的半导体层的SOI衬底中，在nMIS形成区域和pMIS形成区域中的每个半导体层中形成MISFET。 在供电区域中，去除半导体层和绝缘层。 在半导体基板中，形成p型半导体区域，以便包括nMIS形成区域和一个供电区域，并且形成n型半导体区域以便包括pMIS形成区域，而另一个 的供电区域。 在半导体衬底中，形成具有比p型半导体区域低的杂质浓度的p型阱，以便容纳p型半导体区域，并且具有比n型半导体的杂质浓度低的n型阱 区域形成为包含n型半导体区域。

公开(公告)号：US20180247692A1

公开(公告)日：2018-08-30

申请号：US15964864

申请日：2018-04-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C5/06 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US20170345488A1

公开(公告)日：2017-11-30

申请号：US15680269

申请日：2017-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C11/412 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

公开(公告)号：US20170011794A1

公开(公告)日：2017-01-12

申请号：US15274852

申请日：2016-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20160078925A1

公开(公告)日：2016-03-17

申请号：US14942822

申请日：2015-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。