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    SIGNAL GENERATION CIRCUIT AND TEMPERATURE SENSOR
    1.
    发明申请
    SIGNAL GENERATION CIRCUIT AND TEMPERATURE SENSOR 审中-公开

    公开(公告)号：US20180128689A1

    公开(公告)日：2018-05-10

    申请号：US15861819

    申请日：2018-01-04

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shigeki OBAYASHI ,  Hiroki SHIMANO ,  Masataka MINAMI ,  Hiroji OZAKI

    IPC: G01K7/01

    CPC classification number: G01K7/01

    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

    SIGNAL GENERATION CIRCUIT AND TEMPERATURE SENSOR
    2.
    发明申请
    SIGNAL GENERATION CIRCUIT AND TEMPERATURE SENSOR 有权
    信号发生电路和温度传感器

    公开(公告)号：US20150063419A1

    公开(公告)日：2015-03-05

    申请号：US14459356

    申请日：2014-08-14

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Shigeki OBAYASHI ,  Hiroki SHIMANO ,  Masataka MINAMI ,  Hiroji OZAKI

    IPC: G05F1/46 ,  G01K7/00

    CPC classification number: G01K7/01

    Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

    Abstract translation: 提供具有输出电压的稳定时间短的信号发生电路。 在PTAT信号发生电路中，微调电路耦合在第0至第K个二极管的阴极和接地电压之间，第0个二极管的阳极耦合到第一节点，阳极 第一到第K个二极管经由电阻元件耦合到第二节点，第一节点和第二节点被设置为相同的电压，流过第0个二极管的第一电流和流过第0个二极管的第二电流 首先将第K个二极管设定为具有相同的值，并且流过修整电路的第三电流被设置为具有第一电流和第二电流中的每一个的值的2倍的值。

    SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE 审中-公开
    半导体器件和增加电熔丝电阻值的方法

    公开(公告)号：US20170040261A1

    公开(公告)日：2017-02-09

    申请号：US15298484

    申请日：2016-10-20

    Applicant: Renesas Electronics Corporation

    Inventor： Takeshi IWAMOTO ,  Kazushi KONO ,  Masashi ARAKAWA ,  Toshiaki YONEZU ,  Shigeki OBAYASHI

    IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01H85/041

    CPC classification number: H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

    Abstract translation: 一种具有电熔丝结构的半导体器件，其接收电流以允许电熔丝被切割而不损坏保险丝周围的部分。 电熔丝可以电连接在电子电路和冗余电路之间作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权
    半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗

    公开(公告)号：US20140126278A1

    公开(公告)日：2014-05-08

    申请号：US14151581

    申请日：2014-01-09

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

    IPC: G11C11/412 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权
    半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗

    公开(公告)号：US20170011794A1

    公开(公告)日：2017-01-12

    申请号：US15274852

    申请日：2016-09-23

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

    IPC: G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE THAT CAN STABLY PERFORM WRITING AND READING WITHOUT INCREASING CURRENT CONSUMPTION EVEN WITH A LOW POWER SUPPLY VOLTAGE 有权
    半导体存储器件，即使在低功耗电压下也能稳定地执行写入和读取，而不会增加电流消耗

    公开(公告)号：US20160078925A1

    公开(公告)日：2016-03-17

    申请号：US14942822

    申请日：2015-11-16

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

    Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

    Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

    Semiconductor Device and A Method Increasing a Resistance Value of an Electric Fuse
    10.
    发明申请
    Semiconductor Device and A Method Increasing a Resistance Value of an Electric Fuse 有权
    一种提高电保险丝电阻值的半导体器件和方法

    公开(公告)号：US20150303144A1

    公开(公告)日：2015-10-22

    申请号：US14590294

    申请日：2015-01-06

    Applicant: Renesas Electronics Corporation

    Inventor： Takeshi IWAMOTO ,  Kazushi KONO ,  Masashi ARAKAWA ,  Toshiaki YONEZU ,  Shigeki OBAYASHI

    IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

    Abstract translation: 一种具有电熔丝结构的半导体器件，其接收电流以允许电熔丝被切割而不损坏保险丝周围的部分。 电熔丝可以电连接在电子电路和冗余电路之间作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

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