公开(公告)号：US20140293680A1

公开(公告)日：2014-10-02

申请号：US14263307

申请日：2014-04-28

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/417 ,  G11C5/14 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

公开(公告)号：US20190139966A1

公开(公告)日：2019-05-09

申请号：US16239835

申请日：2019-01-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Makoto YABUUCHI ,  Yasumasa TSUKAMOTO ,  Kengo MASUDA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10 ,  H01L27/02 ,  H01L21/265 ,  H01L29/66

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US20180342522A1

公开(公告)日：2018-11-29

申请号：US16014920

申请日：2018-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Makoto YABUUCHI ,  Yasumasa TSUKAMOTO ,  Kengo MASUDA

IPC: H01L27/11 ,  G11C11/412 ,  H01L29/10 ,  H01L29/66 ,  H01L27/02 ,  H01L21/265

CPC classification number: H01L27/11 ,  G11C11/412 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/1083 ,  H01L29/66659

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

公开(公告)号：US20160172023A1

公开(公告)日：2016-06-16

申请号：US15052188

申请日：2016-02-24

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

公开(公告)号：US20170236579A1

公开(公告)日：2017-08-17

申请号：US15586870

申请日：2017-05-04

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/417

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.