知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.02 seconds)

    SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT 审中-公开
    包括负偏压生成电路的半导体器件

    公开(公告)号：US20160027502A1

    公开(公告)日：2016-01-28

    申请号：US14877091

    申请日：2015-10-07

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/41

    Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

    Abstract translation: 半导体器件包括连接到存储单元的位线，产生在写入期间施加到位线的负偏置电压的负偏置电压产生电路和产生基于负偏置基准电压的负偏置基准电压产生单元 基于第一电阻器和第二电阻器之间的电阻比。

    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION
    3.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION 有权
    具有生成芯片识别信息能力的半导体器件

    公开(公告)号：US20160358667A1

    公开(公告)日：2016-12-08

    申请号：US15240863

    申请日：2016-08-18

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

    IPC: G11C29/12 ,  G11C11/417

    CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

    Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

    Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏;测试地址存储单元，被配置为存储测试地址; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权

    公开(公告)号：US20160358645A1

    公开(公告)日：2016-12-08

    申请号：US15239410

    申请日：2016-08-17

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20150029784A1

    公开(公告)日：2015-01-29

    申请号：US14334790

    申请日：2014-07-18

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

    IPC: G11C11/41

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Abstract translation: 提供了一种半导体集成电路器件，其可以抑制开销来产生唯一的ID。 当产生唯一的ID时，SRAM中的存储单元的字线的电位升高到高于SRAM的电源电压，然后降低到SRAM的电源电压以下。 当字线的电位高于SRAM的电源电压时，相同的数据被提供给存储单元的两个位线。 由此，SRAM中的存储单元处于未定义状态，然后变化，以便根据构成存储单元的元件等的特性保持数据。 在SRAM的制造中，存在构成存储单元的元件等的特性的变化。 因此，SRAM中的存储单元根据制造中发生的变化来保存数据。

    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION
    6.
    发明申请
    SEMICONDUCTOR DEVICE HAVING CAPABILITY OF GENERATING CHIP IDENTIFICATION INFORMATION 有权
    具有生成芯片识别信息能力的半导体器件

    公开(公告)号：US20140070212A1

    公开(公告)日：2014-03-13

    申请号：US14022721

    申请日：2013-09-10

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

    IPC: G06K19/07

    CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

    Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns; a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

    Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏; 被配置为存储测试地址的测试地址存储单元; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

    SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT
    7.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT 有权
    包括负偏压生成电路的半导体器件

    公开(公告)号：US20140010027A1

    公开(公告)日：2014-01-09

    申请号：US13935815

    申请日：2013-07-05

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro FUJIWARA

    IPC: G11C7/12

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/41

    Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

    Abstract translation: 半导体器件包括连接到存储单元的位线，产生在写入期间施加到位线的负偏置电压的负偏置电压产生电路和产生基于负偏置基准电压的负偏置基准电压产生单元 基于第一电阻器和第二电阻器之间的电阻比。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20180204613A1

    公开(公告)日：2018-07-19

    申请号：US15919525

    申请日：2018-03-13

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

    IPC: G11C11/419 ,  G11C11/417 ,  G11C17/12 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

Patent Agency Ranking