公开(公告)号：US20170352399A1

公开(公告)日：2017-12-07

申请号：US15613882

申请日：2017-06-05

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato YOKOYAMA ,  Yoshikazu SAITO ,  Shunya NAGATA ,  Toshiaki SANO ,  Takeshi HASHIZUME

IPC: G11C11/405 ,  G11C8/16 ,  G11C7/06 ,  G11C11/406 ,  H03K19/177 ,  G11C11/408

CPC classification number: G11C11/405 ,  G11C7/062 ,  G11C8/16 ,  G11C11/40603 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/32 ,  G11C2029/1202 ,  G11C2207/104 ,  H03K19/1776

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

公开(公告)号：US20210241808A1

公开(公告)日：2021-08-05

申请号：US17158301

申请日：2021-01-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shunya NAGATA ,  Yoshikazu SAITO ,  Takeshi HASHIZUME

IPC: G11C8/10 ,  G11C8/08 ,  G11C7/18 ,  G11C7/06

Abstract: A semiconductor device includes a memory array arranged in a matrix, a plurality of word lines provided corresponding to memory cell rows, a word driver for driving one of the plurality of word lines, a plurality of row select lines connected to the word driver, and a row decoder for outputting a row select signal to the plurality of row select lines based on input row address information. According to the embodiment, the semiconductor device can detect a failure of the address decoder in a simple method.

公开(公告)号：US20180315470A1

公开(公告)日：2018-11-01

申请号：US15914458

申请日：2018-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Takeshi HASHIZUME ,  Toshiaki SANO

IPC: G11C11/417

Abstract: A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.

公开(公告)号：US20180349222A1

公开(公告)日：2018-12-06

申请号：US15984572

申请日：2018-05-21

Applicant: Renesas Electronics Corporation

Inventor： Takeshi HASHIZUME ,  Naoya FUJITA ,  Shunya NAGATA ,  Yoshisato YOKOYAMA ,  Katsumi SHINBO ,  Kouji SATOU

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1048 ,  G11C5/04 ,  G11C11/413 ,  G11C29/52 ,  G11C2029/0411

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.