公开(公告)号：US20200075115A1

公开(公告)日：2020-03-05

申请号：US16540788

申请日：2019-08-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Shinji TANAKA

IPC: G11C29/18 ,  G11C7/22

Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

公开(公告)号：US20190355712A1

公开(公告)日：2019-11-21

申请号：US16528177

申请日：2019-07-31

Applicant: Renesas Electronics Corporation

Inventor： Yuta YOSHIDA ,  Makoto YABUUCHI ,  Yoshisato YOKOYAMA

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/419 ,  H01L27/092 ,  G11C11/418 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.

公开(公告)号：US20170352399A1

公开(公告)日：2017-12-07

申请号：US15613882

申请日：2017-06-05

Applicant: Renesas Electronics Corporation

Inventor： Yoshisato YOKOYAMA ,  Yoshikazu SAITO ,  Shunya NAGATA ,  Toshiaki SANO ,  Takeshi HASHIZUME

IPC: G11C11/405 ,  G11C8/16 ,  G11C7/06 ,  G11C11/406 ,  H03K19/177 ,  G11C11/408

CPC classification number: G11C11/405 ,  G11C7/062 ,  G11C8/16 ,  G11C11/40603 ,  G11C11/4085 ,  G11C11/4087 ,  G11C29/024 ,  G11C29/32 ,  G11C2029/1202 ,  G11C2207/104 ,  H03K19/1776

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

公开(公告)号：US20200342936A1

公开(公告)日：2020-10-29

申请号：US16845929

申请日：2020-04-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Makoto YABUUCHI

IPC: G11C11/418 ,  G11C11/419

Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

公开(公告)号：US20190296734A1

公开(公告)日：2019-09-26

申请号：US16286428

申请日：2019-02-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Toshiaki SANO

IPC: H03K17/14 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412 ,  H03K17/284

Abstract: A MOS transistor is allowed to recover from BTI degradation even when an operation mode signal is inactive. A semiconductor device includes a drive circuit coupled to a controlled circuit via a delay element. The drive circuit includes first and second MOS transistors coupled in series to each other. The first MOS transistor is controlled to be in an OFF state when the operation mode signal is active. When the operation mode signal is inactive, the first MOS transistor is controlled to be in the OFF state at least temporarily while the second MOS transistor is controlled to be in the OFF.

公开(公告)号：US20180053546A1

公开(公告)日：2018-02-22

申请号：US15795704

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Atsushi MIYANISHI ,  Yuichiro ISHII ,  Yoshisato YOKOYAMA

IPC: G11C11/419 ,  G11C11/413 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed.An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

公开(公告)号：US20180315470A1

公开(公告)日：2018-11-01

申请号：US15914458

申请日：2018-03-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA ,  Takeshi HASHIZUME ,  Toshiaki SANO

IPC: G11C11/417

Abstract: A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.

公开(公告)号：US20170194049A1

公开(公告)日：2017-07-06

申请号：US15465300

申请日：2017-03-21

Applicant: Renesas Electronics Corporation

Inventor： Atsushi MIYANISHI ,  Yuichiro ISHII ,  Yoshisato YOKOYAMA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed.An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

公开(公告)号：US20160254062A1

公开(公告)日：2016-09-01

申请号：US15000027

申请日：2016-01-18

Applicant: Renesas Electronics Corporation

Inventor： Atsushi MIYANISHI ,  Yuichiro ISHII ,  Yoshisato YOKOYAMA

IPC: G11C29/04 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C7/04 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  G11C29/02 ,  G11C29/04 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C29/48 ,  G11C29/50

Abstract: When a screening test at a normal temperature is performed instead of a low temperature screening test of SRAM, overkill is reduced and risk of outflow of defects due to local variation is suppressed.An SRAM including a word line, a bit line pair, a memory cell, and a drive circuit that drives the bit line pair is provided with a function that can drive one bit line of the bit line pair at a high level (VDD) potential and drive the other bit line at an intermediate potential (VSS+several tens mV to one handled and several tens mV) a little higher than a low level (VSS) potential for normal writing when writing data into the memory cell.

Abstract translation: 当进行常温下的筛选试验而不是SRAM的低温筛选试验时，过度杀虫剂被降低，并且由于局部变化而导致的缺陷流出的风险被抑制。 包括字线，位线对，存储单元和驱动位线对的驱动电路的SRAM具有能够将位线对的一个位线驱动为高电平（VDD）电位的功能 并在将数据写入存储单元时将其他位线驱动为比正常写入的低电平（VSS）电位稍高的中间电位（VSS +几十mV至几十mV）。

公开(公告)号：US20190293716A1

公开(公告)日：2019-09-26

申请号：US16286447

申请日：2019-02-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshisato YOKOYAMA

IPC: G01R31/317 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: A semiconductor device includes a memory cell array, a plurality of word lines, a plurality of bit line pairs, a column selection circuit coupling a bit line pair in a selected column in the plurality of bit line pairs to first and second output signal lines on the basis of a column selection signal, and a sense amplifier amplifying the voltage difference between the first and second output signal lines. The semiconductor device further includes: a scan flip flop to which the data can be input via a scan chain; and a voltage setting circuit setting the first and second output signal lines to voltage according to the data held in the scan flip flop in a scan test.