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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20180261280A1

    公开(公告)日：2018-09-13

    申请号：US15981355

    申请日：2018-05-16

    Applicant: Renesas Electronics Corporation

    Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

    IPC: G11C11/419 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C7/08 ,  G11C11/418 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20170301664A1

    公开(公告)日：2017-10-19

    申请号：US15512933

    申请日：2015-03-26

    Applicant: Renesas Electronics Corporation

    Inventor： Yuta YOSHIDA ,  Makoto YABUUCHI ,  Yoshisato YOKOYAMA

    IPC: H01L27/02 ,  H01L27/11 ,  H01L23/528 ,  G11C11/418 ,  H01L23/522 ,  G11C11/419 ,  H01L27/092

    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140016391A1

    公开(公告)日：2014-01-16

    申请号：US14026575

    申请日：2013-09-13

    Applicant: Renesas Electronics Corporation

    Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

    IPC: G11C5/06

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

    Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160133315A1

    公开(公告)日：2016-05-12

    申请号：US14981195

    申请日：2015-12-28

    Applicant: Renesas Electronics Corporation

    Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

    IPC: G11C11/419 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

    Abstract translation: 提供了具有减小操作时序的变化的存储单元的半导体器件。 例如，半导体器件设置有与适当的位线相对布置的虚拟位线，以及顺序耦合到虚拟位线的列方向负载电路。 每个列方向负载电路设置有多个固定在截止状态的NMOS晶体管，其中预定的NMOS晶体管具有适当地耦合到任何虚拟位线的源极和漏极。 将与预定NMOS晶体管的扩散层电容相关的负载电容加到虚拟位线，并且对应于负载电容，建立从解码激活信号到虚拟位线信号的延迟时间。 当设置读出放大器的启动定时时，采用虚拟位线信号。

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