公开(公告)号：US20190108876A1

公开(公告)日：2019-04-11

申请号：US16214220

申请日：2018-12-10

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Markoto Yabuuchi ,  Masao Morimoto

IPC: G11C11/419 ,  G11C8/08 ,  G11C8/16 ,  G11C7/22 ,  G11C8/00 ,  G11C7/00 ,  G11C8/18 ,  G11C11/418 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418

Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.