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    SEQUENTIAL VOLTAGE CONTROL FOR A MEMORY DEVICE
    3.
    发明申请
    SEQUENTIAL VOLTAGE CONTROL FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210350861A1

    公开(公告)日：2021-11-11

    申请号：US16870670

    申请日：2020-05-08

    申请人： Micron Technology, Inc.

    发明人： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

    IPC分类号： G11C16/30 ,  G11C16/12 ,  G11C16/32 ,  G11C16/04 ,  G11C7/20

    摘要： Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

    Apparatuses and methods for adjusting timing of signals
    4.
    发明授权
    Apparatuses and methods for adjusting timing of signals 有权

    公开(公告)号：US10312893B2

    公开(公告)日：2019-06-04

    申请号：US15604297

    申请日：2017-05-24

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Yantao Ma

    IPC分类号： H03K5/12 ,  H03K5/05 ,  H03K5/156 ,  H03K5/134

    摘要： Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.

    APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS
    5.
    发明申请
    APPARATUSES AND METHODS FOR PHASE INTERPOLATING CLOCK SIGNALS AND FOR PROVIDING DUTY CYCLE CORRECTED CLOCK SIGNALS 审中-公开

    公开(公告)号：US20180006636A1

    公开(公告)日：2018-01-04

    申请号：US15704868

    申请日：2017-09-14

    申请人： Micron Technology, Inc.

    发明人： Yantao Ma

    IPC分类号： H03K5/156 ,  H03K19/003 ,  H03K5/15 ,  H03K19/013 ,  H03K5/00

    CPC分类号： H03K5/1565 ,  H03K5/15 ,  H03K19/003 ,  H03K19/0136 ,  H03K2005/00052

    摘要： Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals are described. An example apparatus includes a clock generator circuit configured to provide first and second clock signals responsive to an input clock signal. A duty phase interpolator circuit may be coupled to the clock generator circuit and configured to provide a first and second duty cycle corrected interpolated clock signals. A duty cycle adjuster circuit may be coupled to the duty phase interpolator circuit and configured to receive the first and second duty cycle corrected interpolated clock signals and provide a duty cycle corrected clock signal responsive thereto. A duty cycle detector may be coupled to the duty cycle adjuster circuit and configured to detect duty cycle error of the duty cycle corrected clock signal and provide the adjustment signals to correct the duty cycle error.

    CLOCK SIGNAL AND SUPPLY VOLTAGE VARIATION TRACKING
    6.
    发明申请
    CLOCK SIGNAL AND SUPPLY VOLTAGE VARIATION TRACKING 有权
    时钟信号和电源电压变化跟踪

    公开(公告)号：US20160365860A1

    公开(公告)日：2016-12-15

    申请号：US14736005

    申请日：2015-06-10

    申请人： Micron Technology, Inc.

    发明人： Yantao Ma ,  Tyler Gomm

    IPC分类号： H03L7/08 ,  H03L7/089 ,  H03K5/156 ,  H03L7/081

    CPC分类号： H03L7/0802 ,  H03K5/1565 ,  H03L1/00 ,  H03L7/0812 ,  H03L7/0891

    摘要： Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

    摘要翻译： 本文公开的实施例提供了一种装置，包括时钟生成电路，其被配置为产生第一时间段的第一信号和第二时间段的第二信号;电荷泵电路，耦合到时钟发生电路并且被配置为产生第一电压， 至少部分地基于第一时间段和第二时间段的第二电压以及耦合到电荷泵电路的比较电路，所述比较电路被配置为将第一电压和第二电压之间的差与 并且响应于确定第一和第二电压之间的差超过阈值而产生主动跟踪启用信号。

    Measurement initialization circuitry
    7.
    发明授权
    Measurement initialization circuitry 有权

    公开(公告)号：US09419628B2

    公开(公告)日：2016-08-16

    申请号：US14482846

    申请日：2014-09-10

    申请人： Micron Technology, Inc.

    发明人： Aaron Willey ,  Yantao Ma

    IPC分类号： H03L7/06 ,  H03L7/081 ,  G11C7/22 ,  H03L7/08 ,  H03K5/14

    CPC分类号： H03L7/0812 ,  G11C7/222 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0816

    摘要： Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.

    APPARATUSES AND METHODS FOR PROVIDING CLOCK SIGNALS
    8.
    发明申请
    APPARATUSES AND METHODS FOR PROVIDING CLOCK SIGNALS 有权
    提供时钟信号的方法和方法

    公开(公告)号：US20160085260A1

    公开(公告)日：2016-03-24

    申请号：US14958650

    申请日：2015-12-03

    申请人： Micron Technology, Inc.

    发明人： Huy T. Vo ,  Yantao Ma

    IPC分类号： G06F1/06 ,  G06F1/08

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F1/324 ,  G06F1/3275 ,  H03K5/1515 ,  Y02D10/126 ,  Y02D10/14

    摘要： Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.

    摘要翻译： 本文描述了用于提供时钟信号的装置和方法。 示例性装置可以包括时钟发生器电路。 时钟发生器电路可以被配置为在时钟路径中选择性地向多路复用器提供第一和第二中间信号，以在第一模式下工作时提供具有第一频率的输出时钟信号，并且选择性地将第一和第二中间时钟信号提供给 时钟路径中的多路复用器，以在第二模式下操作时提供具有第二频率的输出时钟信号。

    Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated measure initialization circuitry
    9.
    发明授权
    Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated measure initialization circuitry 有权
    使用具有均匀架构和集成度量初始化电路的延迟线来延迟信号的装置和方法

    公开(公告)号：US09264050B2

    公开(公告)日：2016-02-16

    申请号：US14338087

    申请日：2014-07-22

    申请人： Micron Technology, Inc.

    发明人： Yantao Ma

    IPC分类号： H03L7/06 ,  H03L7/08 ,  H03H11/26 ,  H03K5/13 ,  H03L7/081 ,  H03K5/00 ,  G11C7/22 ,  G11C7/04

    CPC分类号： H03L7/08 ,  G11C7/04 ,  G11C7/222 ,  H03H11/26 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0814 ,  H03L7/0816

    摘要： Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

    摘要翻译： 描述了使用延迟线延迟信号的装置和方法。 示例性装置包括控制器，被配置为处于第一模式，设置延迟长度，并且在第二模式中，确定初始延迟。 该装置还包括耦合到控制器并包括延迟元件的延迟线电路。 每个延迟元件包括相同类型的延迟门的延迟门。 延迟线电路被配置为在第一模式中通过一个或多个延迟元件传播信号以提供延迟信号。 延迟线电路还被配置为在第二模式中，通过一个或多个延迟元件传播脉冲信号，并且响应于脉冲信号提供来自一个或多个延迟元件中的每个延迟元件的相应输出信号， 相应的延迟元件。

    Power supply induced signal jitter compensation
    10.
    发明授权
    Power supply induced signal jitter compensation 有权
    电源引起的信号抖动补偿

    公开(公告)号：US09202542B2

    公开(公告)日：2015-12-01

    申请号：US14330893

    申请日：2014-07-14

    申请人： Micron Technology, Inc.

    发明人： Yantao Ma ,  Aaron Willey

    IPC分类号： H03H11/26 ,  G11C7/22 ,  H03K5/156 ,  H03L7/081 ,  H03K5/13

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03H11/265 ,  H03K5/133 ,  H03K5/1565 ,  H03L7/0812

    摘要： Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response.

    摘要翻译： 用于补偿对电源变化敏感的路径元件中的电源引起的信号抖动的电路和方法的示例。 示例包括将输入耦合到输出的信号路径，信号路径包括具有第一延迟的延迟元件和具有第二延迟的偏置控制延迟元件。 延迟元件的第一延迟对施加到其上的功率变化表现出第一响应，并且偏置控制延迟元件的第二延迟对施加的功率变化表现出第二响应，使得第二响应至少部分地为 第一反应。