公开(公告)号：US11889673B2

公开(公告)日：2024-01-30

申请号：US17698336

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangshin Han ,  Taehyung Kim

IPC: G11C11/00 ,  H10B10/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419

Abstract: An integrated circuit includes: a dual port Static Random Access Memory (SRAM) cell including a plurality of transistors; a bit line pair connected to the dual port SRAM cell, the bit line pair including a first bit line and a second bit line spaced apart from each other in a first direction and extending in a second direction perpendicular to the first direction; a power line group including a plurality of power lines spaced apart from each other in the first direction, spaced apart from the bit line pair placed in the first direction, and extending in the second direction, the power line group being configured to apply a voltage to the dual-port SRAM cell; and a first word line provided between the first bit line and the second bit line and connected to the dual port SRAM cell.

公开(公告)号：US12046653B2

公开(公告)日：2024-07-23

申请号：US17501454

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US20240128164A1

公开(公告)日：2024-04-18

申请号：US18475290

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngrok Park ,  Hoyoung Tang ,  Taehyung Kim ,  Sangshin Han

IPC: H01L23/48 ,  G06F30/392 ,  G06F30/394 ,  H01L23/528

CPC classification number: H01L23/481 ,  G06F30/392 ,  G06F30/394 ,  H01L23/5283 ,  H01L23/5286

Abstract: An integrated circuit may include a bit cell array including a plurality of bit cells and a peripheral region including a peripheral circuit. The peripheral region may include a plurality of devices over a substrate, at least one pattern configured to provide a first voltage to at least one of the plurality of devices, at least one power line extending under the substrate, and at least one first via passing through the substrate in a vertical direction in the peripheral region and electrically connecting the at least one pattern to the at least one power line.

公开(公告)号：US12165701B2

公开(公告)日：2024-12-10

申请号：US17824464

申请日：2022-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun Lim ,  Taehyung Kim ,  Sangshin Han

IPC: G11C11/41 ,  G11C11/419 ,  H01L27/02 ,  H10B10/00

Abstract: A semiconductor device includes a first memory column group including a plurality of memory columns in which a plurality of bit cells are disposed; and a first peripheral column group including a plurality of peripheral columns in which a plurality of standard cells are disposed, wherein the plurality of standard cells are configured to perform an operation of reading/writing data from/to the plurality of bit cells through a plurality of bit lines, wherein the first memory column group and the first peripheral column group correspond to each other in a column direction, and wherein at least one of the plurality of peripheral columns has a cell height different from cell heights of the other peripheral columns, the cell height being measured in a row direction in which a gate line is extended.

公开(公告)号：US20240332390A1

公开(公告)日：2024-10-03

申请号：US18736647

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US20220140099A1

公开(公告)日：2022-05-05

申请号：US17501454

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop KIM ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/11 ,  H01L27/092

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.