公开(公告)号：US11476257B2

公开(公告)日：2022-10-18

申请号：US17371522

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee ,  Seunghun Lee ,  Sangyeop Baeck ,  Seunghan Park ,  Hyejin Lee

IPC: G11C5/06 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

Abstract: An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.

公开(公告)号：US12046653B2

公开(公告)日：2024-07-23

申请号：US17501454

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US20240332390A1

公开(公告)日：2024-10-03

申请号：US18736647

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US20220140099A1

公开(公告)日：2022-05-05

申请号：US17501454

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop KIM ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/11 ,  H01L27/092

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US12080348B2

公开(公告)日：2024-09-03

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US20230178151A1

公开(公告)日：2023-06-08

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.