公开(公告)号：US12046653B2

公开(公告)日：2024-07-23

申请号：US17501454

申请日：2021-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.

公开(公告)号：US20240332390A1

公开(公告)日：2024-10-03

申请号：US18736647

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bonyeop Kim ,  Taehyung Kim ,  Sangshin Han ,  Sangyeop Baeck

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H10B10/00

CPC classification number: H01L29/42392 ,  H01L27/0924 ,  H01L29/0673 ,  H10B10/12

Abstract: An integrated circuit includes: a memory cell block including a plurality of bitcells; and an input and output (I/O) block including a plurality of gate-all-around (GAA) transistors connected to the bitcells, wherein the I/O block includes a plurality of active regions disposed separately from one another in a first direction, each of which extends in a second direction that is vertical to the first direction, and in which the GAA transistors are formed, a plurality of power rails disposed separately from one another in the first direction, and configured to provide power to the GAA transistors, and a plurality of signal lines disposed between the power rails, and configured to provide signals to the GAA transistors, a first number of bitcells among the bitcells are connected to the GAA transistors formed in a second number of active regions among the active regions, and the second number is twice the first number.