公开(公告)号：US11875844B2

公开(公告)日：2024-01-16

申请号：US17577198

申请日：2022-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  Younghwan Park ,  Jaesung Choi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: Disclosed is a static random access memory (SRAM) device. According to example embodiments of the present disclosure, a control logic of the SRAM device may include a tracking circuit connected with metal lines for tracking the number of columns of a memory cell array and the number of rows of the memory cell array. By the tracking circuit, a length of word lines of the memory cell array and a length of bit lines of the memory cell array may be tracked. The control logic of the SRAM device may generate control pulses optimized for the size of the memory cell array, based on a tracking result(s) of the tracking circuit. Accordingly, a power and a time necessary for a write operation and a read operation may be reduced.

公开(公告)号：US11183233B2

公开(公告)日：2021-11-23

申请号：US16566002

申请日：2019-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US11127730B2

公开(公告)日：2021-09-21

申请号：US16539474

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  JaeSeung Choi ,  Hyunsu Choi ,  SangShin Han

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/11 ,  H01L27/092 ,  G06F30/398 ,  H01L29/78 ,  G06F30/392 ,  G06F30/394

Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

公开(公告)号：US20250046366A1

公开(公告)日：2025-02-06

申请号：US18420456

申请日：2024-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong KIM ,  Inhak Lee ,  Jaesung Choi

IPC: G11C11/418 ,  G11C11/419

Abstract: A memory device includes a cell array including a plurality of static random-access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input/output circuit connected to a plurality of bit lines of the cell array and connected to a sub-power line configured to supply cell voltage to the plurality of SRAM cells; and a word line pulse generator configured to generate a word line pulse with a first pulse width that varies based on the row address and to provide the word line pulse to the row decoder.

公开(公告)号：US12080348B2

公开(公告)日：2024-09-03

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US20230178151A1

公开(公告)日：2023-06-08

申请号：US17820995

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuwon Choi ,  Suk Youn ,  Chanho Lee ,  Taehyung Kim ,  Sangyeop Baeck ,  Inhak Lee

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

公开(公告)号：US11854610B2

公开(公告)日：2023-12-26

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  H10B10/00 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H01L23/5286 ,  H01L27/092 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US11581038B2

公开(公告)日：2023-02-14

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20180294018A1

公开(公告)日：2018-10-11

申请号：US15840601

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeop Baeck ,  Inhak Lee ,  SangShin Han ,  Tae-Hyung Kim ,  JaeSeung Choi ,  Sunghyun Park ,  Hyunsu Choi

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/4096 ,  G11C7/12 ,  G11C11/412 ,  G11C5/14 ,  G11C8/08 ,  G11C8/16

Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

公开(公告)号：US20240412771A1

公开(公告)日：2024-12-12

申请号：US18507444

申请日：2023-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiryong Kim ,  Jungmyung Kang ,  Inhak Lee ,  Jaesung Choi ,  Jeonseung Kang ,  Duhwi Kim ,  Jaeyoung Kim

IPC: G11C11/4074 ,  G11C11/4072 ,  G11C11/4096

Abstract: An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.