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    SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250014991A1

    公开(公告)日：2025-01-09

    申请号：US18446430

    申请日：2023-08-08

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Chen Sun

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06

    Abstract: Provided is a semiconductor device including a conductive layer, a stop layer, a second dielectric layer disposed on a first dielectric layer and a resistor. The resistor includes a part of the conductive layer, a first strip-like contact, a second strip-like contact, a first auxiliary contact, a second auxiliary contact, a third auxiliary contact and a fourth auxiliary contact. The first strip-like contact and the second strip-like contact respectively extend through the second dielectric layer and the stop layer, and are electrically connected to the conductive layer. The first auxiliary contact and the second auxiliary contact sandwich the first strip-like contact therebetween, extend through the second dielectric layer, and are electrically connected to the conductive layer. The third auxiliary contact and the fourth auxiliary contact sandwich the second strip-like contact therebetween, extend through the second dielectric layer and are electrically connected to the conductive layer.

    DESIGN METHOD OF SHUTTLE MASK
    2.
    发明公开
    DESIGN METHOD OF SHUTTLE MASK 审中-公开

    公开(公告)号：US20240202417A1

    公开(公告)日：2024-06-20

    申请号：US18179391

    申请日：2023-03-07

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Chen Sun ,  En-Chiuan Liou

    IPC: G06F30/392 ,  G03F1/70

    CPC classification number: G06F30/392 ,  G03F1/70

    Abstract: A design method of a shuttle mask including the following steps is provided. A first integrated circuit (IC) design is provided in a first chip region, and a second IC design is provided in a second chip region. The first IC design includes first main patterns. The second IC design includes second main patterns. First dummy insertion patterns are added in the first chip region, and second dummy insertion patterns are added in the second chip region. The first main patterns and the first dummy insertion patterns are separated from each other. The first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns. The second main patterns and the second dummy insertion patterns are separated from each other. The second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.

    STATIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
    4.
    发明公开
    STATIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240284651A1

    公开(公告)日：2024-08-22

    申请号：US18123992

    申请日：2023-03-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun

    IPC: H10B10/00

    CPC classification number: H10B10/12

    Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of forming a first fin-shaped structure for a first pull-down (PD) transistor on a substrate, forming a second fin-shaped structure for a second PD transistor on the substrate, forming a third fin-shaped structure for a first pass gate (PG) transistor on the substrate, and forming a fourth fin-shaped structure for a second PG transistor on the substrate. Preferably, the first fin-shaped structure and the second fin-shaped structure include a first recess therebetween and the third fin-shaped structure and the fourth fin-shaped structure include no recess therebetween.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    5.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230326792A1

    公开(公告)日：2023-10-12

    申请号：US17740377

    申请日：2022-05-10

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun

    IPC: H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/76897 ,  H01L23/5226 ,  H01L21/76831

    Abstract: A method for fabricating a semiconductor device includes the steps of first forming an active device having a gate structure and a source/drain region on a substrate, forming an interlayer dielectric (ILD) layer on the active device, removing part of the ILD layer to form a contact hole on the active device without exposing the active device and the bottom surface of the contact hole is higher than a top surface of the gate structure, and then forming a metal layer in the contact holt to form a floating contact plug.

    Mask and method of forming pattern
    8.
    发明授权
    Mask and method of forming pattern 有权

    公开(公告)号：US10983428B2

    公开(公告)日：2021-04-20

    申请号：US15978215

    申请日：2018-05-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh

    IPC: G06F30/39 ,  G03F1/36

    Abstract: A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.

    ALIGNMENT MARK AND MEASUREMENT METHOD THEREOF
    10.
    发明申请
    ALIGNMENT MARK AND MEASUREMENT METHOD THEREOF 审中-公开

    公开(公告)号：US20190067204A1

    公开(公告)日：2019-02-28

    申请号：US15715184

    申请日：2017-09-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh ,  Fan-Wei Lin

    IPC: H01L23/544 ,  H01L21/66 ,  G01B21/24

    Abstract: The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.

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