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公开(公告)号：US11664366B2
公开(公告)日：2023-05-30
申请号：US17481300
申请日：2021-09-21
发明人： Yu-Cheng Tung
IPC分类号： H01L21/8238 , H01L27/02 , H01L29/66 , H01L29/78 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/82385 , H01L21/823821 , H01L21/823842 , H01L27/0924 , H01L29/66795 , H01L29/785 , H10B10/12
摘要： A layout of a semiconductor device and a method of forming a semiconductor device, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.
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公开(公告)号：US20210327706A1
公开(公告)日：2021-10-21
申请号：US17359634
申请日：2021-06-27
发明人： Feng-Yi Chang , Fu-Che Lee , Yu-Cheng Tung
IPC分类号： H01L21/027 , H01L21/033 , G03F7/26 , H01L27/108 , G03F7/16 , G03F7/20
摘要： A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.
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公开(公告)号：US11081353B2
公开(公告)日：2021-08-03
申请号：US16174237
申请日：2018-10-29
发明人： Feng-Yi Chang , Fu-Che Lee , Yu-Cheng Tung
IPC分类号： H01L21/027 , H01L21/033 , G03F7/26 , H01L27/108 , G03F7/16 , G03F7/20
摘要： A method of manufacturing a semiconductor device includes the following steps. A first patterned photoresist layer is formed on a substrate. A second patterned photoresist layer is formed on the substrate after the first patterned photoresist layer is formed, wherein the first patterned photoresist layer and the second patterned photoresist layer are arranged alternatively. A liner is formed to cover sidewalls of the first patterned photoresist layer and the second patterned photoresist layer. The present invention also provides a semiconductor device, including a plurality of pillars being disposed on a layer, wherein the layer includes first recesses and second recesses, wherein the depths of the first recesses are less than the depths of the second recesses.
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公开(公告)号：US10763264B2
公开(公告)日：2020-09-01
申请号：US16571202
申请日：2019-09-16
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC分类号： H01L27/108 , G11C11/401
摘要： The present invention provides a method for forming a dynamic random access memory (DRAM) structure, the method including: firstly, a substrate is provided, a cell region and a peripheral region are defined on the substrate, a plurality of buried word lines is then formed in the cell region of the substrate, next, a shallow trench isolation structure is formed in the peripheral region adjacent to the cell region, wherein a concave top surface is formed on the shallow trench isolation structure, afterwards, a first dummy bit line gate is formed within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate is formed in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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公开(公告)号：US10670958B2
公开(公告)日：2020-06-02
申请号：US15937825
申请日：2018-03-27
发明人： Ying-Chiao Wang , Yu-Cheng Tung , Li-Wei Feng , Chien-Ting Ho
IPC分类号： G03F1/36 , G03F7/20 , H01L27/108
摘要： A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.
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公开(公告)号：US20200043733A1
公开(公告)日：2020-02-06
申请号：US16136265
申请日：2018-09-20
发明人： Feng-Yi Chang , Yu-Cheng Tung , Fu-Che Lee
IPC分类号： H01L21/033 , H01L27/108
摘要： A semiconductor device and a method of forming the same, the semiconductor includes a substrate and a material disposed on the substrate. The material layer includes plural first patterns arranged parallel and separately in an array within a first region of the substrate, and plural second patterns parallel and separately disposed at two opposite sides of the first patterns, and plural third patterns parallel and separately disposed at another two opposite sides of the first patterns, wherein each of the third patterns has a relative greater dimension than that of each of the first patterns.
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公开(公告)号：US10553577B2
公开(公告)日：2020-02-04
申请号：US15951129
申请日：2018-04-11
发明人： Yu-Cheng Tung
IPC分类号： H01L27/02 , H01L27/11 , H01L29/66 , H01L29/78 , H01L21/8238
摘要： A layout of a semiconductor device, a semiconductor device and a method of forming the same, the semiconductor device include a first fin and a second fin disposed on a substrate, a gate and a spacer. The first fin and the second fin both include two opposite edges, and the gate completely covers the two opposite edges of the first fin and only covers one sidewall of the two opposite edges of the second fin. The spacer is disposed at two sides of the gate, and the spacer covers another sidewall of the two opposite edges of the second fin.
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公开(公告)号：US10535610B2
公开(公告)日：2020-01-14
申请号：US16003090
申请日：2018-06-07
发明人： Feng-Yi Chang , Fu-Che Lee , Yi-Wang Zhan , Chia-Liang Liao , Yu-Cheng Tung , Chien-Hao Chen , Chia-Hung Wang
IPC分类号： H01L23/544 , H01L27/108 , H01L21/311
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a substrate having a scribe line region. A material layer is formed on the scribe line region and has a rectangular region defined therein. The rectangular region has a pair of first edges parallel with a widthwise direction of the scribe line region and a pair of second edges parallel with a lengthwise direction of the scribe line region. A pair of first alignment features is formed in the material layer along the first edges, and a pair of second alignment features is formed in the material layer along the second edges. The space between the pair of first alignment features is larger than a space between the pair of the second alignment features.
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公开(公告)号：US20190393099A1
公开(公告)日：2019-12-26
申请号：US16562454
申请日：2019-09-06
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang
IPC分类号： H01L21/8234 , H01L29/08 , H01L29/06 , H01L27/088 , H01L27/12 , H01L21/84
摘要： A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.
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公开(公告)号：US20190273083A1
公开(公告)日：2019-09-05
申请号：US15936396
申请日：2018-03-26
发明人： En-Chiuan Liou , Yu-Cheng Tung , Chih-Wei Yang , Sho-Shen Lee
IPC分类号： H01L27/108 , G11C11/401
摘要： The present invention provides a dynamic random access memory structure, comprising a substrate defining a cell region and a peripheral region on the substrate, a shallow trench isolation structure located in the peripheral region adjacent to the cell region, wherein the shallow trench isolation structure has a concave top surface, a first dummy bit line gate located within the shallow trench isolation structure of the peripheral area, and a second dummy bit line gate located in the cell region and adjacent to the first dummy bit line gate, wherein a top surface of the first dummy bit line gate is lower than a top surface of the second dummy bit line gate.
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