公开(公告)号：US20240349512A1

公开(公告)日：2024-10-17

申请号：US18635072

申请日：2024-04-15

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jae-Joon KIM ,  Munhyeon KIM

IPC分类号： H10B53/30

CPC分类号： H10B53/30

摘要： A memory using ferroelectric metal field-effect transistors includes a drain, a source, and a gate formed on a substrate, a gate contact formed on an upper portion of the gate, and a ferroelectric layer disposed between the gate contact and the gate and configured to surround the gate contact, wherein the gate, the ferroelectric layer, and the gate contact operate as a capacitor having a metal-ferroelectric layer-metal (MFM) structure.

公开(公告)号：US20240349477A1

公开(公告)日：2024-10-17

申请号：US18635211

申请日：2024-04-15

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jae-Joon KIM ,  Munhyeon KIM

IPC分类号： H10B12/00

CPC分类号： H10B12/00

摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor including a second gate extending in a second direction perpendicular to the first direction and formed on an upper portion of the first transistor, and a storage node configured to connect a first gate of the first transistor to a drain of the second transistor and storing data.

公开(公告)号：US20240347105A1

公开(公告)日：2024-10-17

申请号：US18635268

申请日：2024-04-15

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jae-Joon KIM ,  Munhyeon KIM

IPC分类号： G11C11/419 ,  G11C5/06 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC分类号： G11C11/419 ,  G11C5/063 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  H10B10/125

摘要： A random access memory includes a first transistor including a first gate extending in a first direction, a second transistor disposed on a same plane as the first transistor and including a second gate extending in the first direction, a third transistor including a third gate extending in a second direction perpendicular to the first direction and formed on the first transistor, a fourth transistor including a fourth gate extending in the second direction and formed on the second transistor, a first storage node connecting the first gate of the first transistor to a drain of the third transistor and storing data, and a second storage node connecting the second gate of the second transistor to a drain of the fourth transistor and storing data.