公开(公告)号：US20240355891A1

公开(公告)日：2024-10-24

申请号：US18753781

申请日：2024-06-25

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US20240355890A1

公开(公告)日：2024-10-24

申请号：US18136991

申请日：2023-04-20

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC分类号： H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US20240321978A1

公开(公告)日：2024-09-26

申请号：US18125456

申请日：2023-03-23

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Baofu Zhu ,  Charles H. Wallace ,  Clifford J. Engel ,  Gary Allen ,  Saurabh Acharya ,  Thomas Obrien

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC分类号： H01L29/41733 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

摘要： Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.

公开(公告)号：US20240321872A1

公开(公告)日：2024-09-26

申请号：US18125447

申请日：2023-03-23

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Thomas Obrien ,  Krishna Ganesan ,  Ankit Kirit Lakhani ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Clifford J. Engel ,  Baofu Zhu ,  Meenakshisundaram Ramanathan

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

摘要： Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.

公开(公告)号：US20240321685A1

公开(公告)日：2024-09-26

申请号：US18125430

申请日：2023-03-23

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Charles H. Wallace

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L21/823481 ,  H01L27/088

摘要： Techniques are provided herein to form semiconductor devices arranged between a gate cut on one side and a deep backside via on the other side. A row of semiconductor devices each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Each semiconductor device may be separated from an adjacent semiconductor device along the second direction by either a gate cut or a deep backside via. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure and the deep backside via may include a conductive layer and a dielectric barrier that also extend through at least an entire thickness of the gate structure. Each semiconductor device may include a gate cut on one side and a deep backside via on the other side.