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1.发明公开公开(公告)号：US20240363633A1
公开(公告)日：2024-10-31
申请号：US18470684
申请日：2023-09-20
发明人： MYUNG YANG , Seungchan YUN , Sooyoung Park , Jaehong Lee , KANG-ILL SEO
IPC分类号： H01L27/092 , H01L21/822 , H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L27/0922 , H01L21/8221 , H01L21/823807 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696 , H03K17/687
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor on a substrate. The transistor may include: a pair of thin semiconductor layers spaced apart from each other; a channel region between the pair of thin semiconductor layers; a gate electrode on the pair of thin semiconductor layers and the channel region; and a gate insulator separating the gate electrode from both the pair of thin semiconductor layers and the channel region. A side surface of the channel region may be recessed with respect to side surfaces of the pair of thin semiconductor layers and may define a recess between the pair of thin semiconductor layers. A portion of the gate insulator and/or a portion of the gate electrode may be in the recess.
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2.发明公开公开(公告)号：US20240136354A1
公开(公告)日：2024-04-25
申请号：US18171754
申请日：2023-02-21
发明人： KEUMSEOK PARK , SOOYOUNG PARK , JAEJIK BAEK , KANG-ILL SEO
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/06 , H01L29/08 , H01L29/786
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823418 , H01L29/0673 , H01L29/0847 , H01L29/78696
摘要： Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate and a transistor stack on the substrate, the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate and the second transistor and the first transistor may include first and second source/drain regions, a first channel region between the first and second source/drain regions, and a first gate structure on the first channel region. A lower surface of the first source/drain region may be higher than a lower surface of the first gate structure relative to the substrate.
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公开(公告)号：US20240072060A1
公开(公告)日：2024-02-29
申请号：US18499258
申请日：2023-11-01
发明人： BYOUNGHAK HONG , SEUNGHYUN SONG , KI-IL KIM , GUNHO JO , KANG-ILL SEO
IPC分类号： H01L27/12 , H01L21/822 , H01L21/8234 , H01L21/84 , H01L27/088
CPC分类号： H01L27/1203 , H01L21/8221 , H01L21/823412 , H01L21/823456 , H01L21/84 , H01L27/088
摘要： Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.
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公开(公告)号：US20210111269A1
公开(公告)日：2021-04-15
申请号：US16794358
申请日：2020-02-19
发明人： Hwi Chan JUN , KANG-ILL SEO , Jeong Hyuk YIM
摘要： Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.
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5.发明公开公开(公告)号：US20240363491A1
公开(公告)日：2024-10-31
申请号：US18240675
申请日：2023-08-31
发明人： SEUNGCHAN YUN , WONHYUK HONG , PANJAE PARK , KANG-ILL SEO
IPC分类号： H01L23/48 , H01L21/768 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L23/481 , H01L21/76898 , H01L21/823475 , H01L27/088 , H01L29/0673 , H01L29/41733 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor comprising a source/drain region on a substrate; a backside power rail spaced apart from the source/drain region; and a power contact that is between the source/drain region and the backside power rail and electrically connects the source/drain region to the backside power rail. The substrate may be between the source/drain region and the backside power rail, and a centerline in a width direction of the source/drain region is angled with respect to a centerline in a width direction of the power contact.
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6.发明公开公开(公告)号：US20230352408A1
公开(公告)日：2023-11-02
申请号：US17936106
申请日：2022-09-28
发明人： MYUNGHOON JUNG , WONHYUK HONG , INCHAN HWANG , GUNHO JO , KANG-ILL SEO
IPC分类号： H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/775 , H01L21/8238 , H01L29/66
CPC分类号： H01L23/5286 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/41733 , H01L29/775 , H01L21/823807 , H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/66439
摘要： Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.
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公开(公告)号：US20230352399A1
公开(公告)日：2023-11-02
申请号：US17822246
申请日：2022-08-25
发明人： JAEMYUNG CHOI , KANG-ILL SEO , JANGGEUN LEE
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/768
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower metal via, an upper metal via, a lower metal wire comprising a lower surface contacting the lower metal via and an upper surface contacting the upper metal via, and an upper metal wire on the upper metal via. The upper metal via is between the lower metal wire and the upper metal wire, and each of the lower metal via, the lower metal wire and the upper metal via comprises ruthenium (Ru) or molybdenum (Mo).
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公开(公告)号：US20170103983A1
公开(公告)日：2017-04-13
申请号：US15387022
申请日：2016-12-21
发明人： HYUN-JAE KANG , JIN-WOOK LEE , KANG-ILL SEO , YONG-MIN CHO
IPC分类号： H01L27/088 , H01L23/522 , H01L21/8234 , H01L27/02 , H01L23/528 , H01L23/532
CPC分类号： H01L27/0886 , G03F7/70 , H01L21/0274 , H01L21/32136 , H01L21/32139 , H01L21/76816 , H01L21/76877 , H01L21/76895 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L27/0207
摘要： Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.
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9.发明公开公开(公告)号：US20240332185A1
公开(公告)日：2024-10-03
申请号：US18454832
申请日：2023-08-24
发明人： TAE SUN KIM , WONHYUK HONG , JONGJIN LEE , KANG-ILL SEO
IPC分类号： H01L23/528 , H01L21/768 , H01L29/417
CPC分类号： H01L23/5286 , H01L21/76895 , H01L29/41766
摘要： Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a backside power distribution network structure (BSPDNS), a logic device region and a passive device region on the BSPDNS, a backside insulating layer including a first portion extending between the BSPDNS and the logic device region and a second portion extending between the BSPDNS and the passive device region, the passive device region including a semiconductor layer that is in the backside insulating layer, and a dam separating the first portion of the backside insulating layer from the semiconductor layer of the passive device region.
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公开(公告)号：US20240145479A1
公开(公告)日：2024-05-02
申请号：US18406345
申请日：2024-01-08
发明人： BYOUNGHAK HONG , SEUNGHYUN SONG , MYUNGGIL KANG , KANG-ILL SEO
IPC分类号： H01L27/12 , G01R27/02 , H01L23/535
CPC分类号： H01L27/1203 , G01R27/02 , H01L23/535 , H01L27/1211
摘要： Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.
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