公开(公告)号：US20210057536A1

公开(公告)日：2021-02-25

申请号：US16829372

申请日：2020-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOOHYUN LEE ,  HEONJONG SHIN ,  MINCHAN GWAK ,  HYUNHO PARK ,  SUNGHUN JUNG ,  YONGSIK JEONG ,  SANGWON JEE ,  INCHAN HWANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

公开(公告)号：US20230352408A1

公开(公告)日：2023-11-02

申请号：US17936106

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： MYUNGHOON JUNG ,  WONHYUK HONG ,  INCHAN HWANG ,  GUNHO JO ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/66439

Abstract: Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

公开(公告)号：US20240213249A1

公开(公告)日：2024-06-27

申请号：US18512094

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHOON HWANG ,  KYUNGHO KIM ,  BYUNGHO MOON ,  KYUNGHEE CHO ,  DOYOUNG CHOI ,  INCHAN HWANG

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823871 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a lower insulating line extending in a first direction, a plurality of lower channel lines over the lower insulating line, first and second lower gate lines respectively on opposing sides of the lower insulating line and opposing sides of one of the lower channel lines, a third lower gate line extending around upper and lower surfaces of the one of the lower channel line and connecting the first and second lower gate lines to each other, an outer gate line arranged under the lower insulating line and contacting the first and second lower gate lines, an upper insulating line over an upper surface of each lower channel line, a plurality of upper channel lines over the upper insulating line, and an upper gate line extending around one of the upper channel lines.

公开(公告)号：US20180083002A1

公开(公告)日：2018-03-22

申请号：US15442859

申请日：2017-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGHWA KIM ,  KYUNGIN CHOI ,  HWICHAN JUN ,  INCHAN HWANG

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/768 ,  H01L21/823431 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5283 ,  H01L27/0207 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.

公开(公告)号：US20240145567A1

公开(公告)日：2024-05-02

申请号：US18329830

申请日：2023-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： INCHAN HWANG ,  MYUNGIL KANG ,  DONGHOON HWANG ,  KYUNGHO KIM ,  SUNGWOO JANG ,  KYUNG HEE CHO

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes: an active area that protrudes from an upper surface of a substrate and extends parallel to the upper surface of the substrate; an element isolating area formed on the substrate and around the active area; a channel formed on an upper surface of the active area; a gate structure that surrounds at least two surfaces of the channel; a spacer formed on both sidewalls of the gate structure; and a source/drain layer in contact with both sidewalls of the channel and insulated from the gate structure by the spacer. The gate structure includes, in a cross-section, a first portion whose width in a first direction increases from an upper portion of the gate structure toward a lower portion closer to the substrate, and a second portion whose width in the first direction remains the same or decreases below the first portion.

公开(公告)号：US20220020860A1

公开(公告)日：2022-01-20

申请号：US17488443

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOOHYUN LEE ,  HEONJONG SHIN ,  MINCHAN GWAK ,  HYUNHO PARK ,  SUNGHUN JUNG ,  YONGSIK JEONG ,  SANGWON JEE ,  INCHAN HWANG

IPC: H01L29/45 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.