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    Structure to prevent deep trench moat charging and moat isolation fails
    1.
    发明授权
    Structure to prevent deep trench moat charging and moat isolation fails 有权
    结构防止深沟槽护城河充电和护城河隔离失效

    公开(公告)号：US09490223B2

    公开(公告)日：2016-11-08

    申请号：US14566773

    申请日：2014-12-11

    申请人： GLOBALFOUNDRIES INC.

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L21/70 ,  H01L23/00 ,  H01L29/06 ,  H01L21/762

    CPC分类号： H01L23/564 ,  H01L21/26586 ,  H01L21/743 ,  H01L21/76229 ,  H01L21/84 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/66181 ,  H01L29/945 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure is provided that includes a semiconductor on insulator (SOI) substrate comprising a bottom semiconductor layer, an epitaxial semiconductor layer present on the bottom semiconductor layer, a buried insulator layer present on the epitaxial semiconductor layer, and a top semiconductor layer present on the buried insulator layer. A deep trench moat (DTMOAT) is disposed in the SOI substrate and has a bottom surface contacting a dopant region of the bottom semiconductor layer. A moat contact electrically connecting the DTMOAT to the epitaxial semiconductor layer of the SOI substrate. Charges accumulated in the DTMOAT can be discharged through the heavily doped epitaxial semiconductor layer to ground, thus preventing the DTMOAT failure caused by the process-induced charge accumulation.

    摘要翻译： 提供一种半导体结构，其包括半导体绝缘体（SOI）衬底，其包括底部半导体层，存在于底部半导体层上的外延半导体层，存在于外延半导体层上的掩埋绝缘体层以及存在于外部半导体层上的顶部半导体层 埋层绝缘体层。 深沟槽沟（DTMOAT）设置在SOI衬底中并具有与底部半导体层的掺杂区接触的底面。 将DTMOAT电连接到SOI衬底的外延半导体层的护套接点。 在DTMOAT中累积的电荷可以通过重掺杂的外延半导体层放电到地面，从而防止由过程引起的电荷积累引起的DTMOAT故障。

    NANOCHANNEL ELECTRODE DEVICES
    7.
    发明申请
    NANOCHANNEL ELECTRODE DEVICES 审中-公开
    NANOCHANNEL电极器件

    公开(公告)号：US20160116435A1

    公开(公告)日：2016-04-28

    申请号：US14987329

    申请日：2016-01-04

    申请人： GLOBALFOUNDRIES INC.

    发明人： Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Chengwen Pei ,  Geng Wang

    IPC分类号： G01N27/414 ,  H01L29/08

    CPC分类号： G01N27/4145 ,  G01N33/48721 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/413

    摘要： A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string.

    摘要翻译： 可以通过在基板上形成相互间隔一定距离的一对半导体翅片来制造纳米尺寸的电极装置。 该对半导体散热片可以用作一对电极，该电极可被偏置以检测通过纳米级串的通过的漏电流。 在一对半导体鳍片之间形成具有均匀间隔距离的纳米通道。 纳米通道可以由形成在一对半导体鳍片上的一对凸起的有源区域之间或在该对半导体鳍片的近侧壁之间的间隙限定。 通过在纳米通道的区域下方的衬底的部分形成开口，以使得能够通过纳米级的串。

    Asymmetric stressor DRAM
    8.
    发明授权
    Asymmetric stressor DRAM 有权
    不对称应力源DRAM

    公开(公告)号：US09240482B2

    公开(公告)日：2016-01-19

    申请号：US14476897

    申请日：2014-09-04

    申请人： GLOBALFOUNDRIES INC.

    发明人： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

    IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L27/108

    CPC分类号： H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

    摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

    摘要翻译： 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平坦化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

    LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION
    9.
    发明申请
    LOW ENERGY ION IMPLANTATION OF A JUNCTION BUTTING REGION 审中-公开
    一个连接区域的低能量离子植入

    公开(公告)号：US20150348974A1

    公开(公告)日：2015-12-03

    申请号：US14820667

    申请日：2015-08-07

    申请人： GLOBALFOUNDRIES INC.

    发明人： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC分类号： H01L27/108 ,  H01L29/06

    CPC分类号： H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

    摘要： The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

    摘要翻译： 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。