公开(公告)号：US10290574B2

公开(公告)日：2019-05-14

申请号：US15408883

申请日：2017-01-18

申请人： GLOBALFOUNDRIES INC.

发明人： Geng Wang ,  Kangguo Cheng ,  Chengwen Pei ,  Juntao Li

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L21/822 ,  H01L23/528 ,  H01L21/768

摘要： Various embodiments include three-dimensional (3D) integrated circuit (IC) structures and methods of forming such structures. In some cases, a 3D IC structure includes: a substrate; a first set of transistors overlying the substrate; a first inter-level dielectric (ILD) overlying the first set of transistors and the substrate; a dielectric overlying the first ILD; a semiconductor layer overlying the dielectric; a second set of transistors overlying the semiconductor layer; a capacitor embedded within the dielectric; and a first contact extending through the semiconductor layer and the dielectric to contact one layer of the capacitor, and a second contact extending through the semiconductor layer and the dielectric to contact a second, distinct layer of the capacitor.

公开(公告)号：US20180061969A1

公开(公告)日：2018-03-01

申请号：US15793419

申请日：2017-10-25

申请人： GLOBALFOUNDRIES INC.

发明人： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/22 ,  H01L21/311 ,  H01L21/285 ,  H01L21/225 ,  H01L29/207

CPC分类号： H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L23/48 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L2223/00

摘要： Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US09634084B1

公开(公告)日：2017-04-25

申请号：US15040477

申请日：2016-02-10

申请人： GLOBALFOUNDRIES INC.

发明人： Christopher D. Sheraw ,  Chengwen Pei ,  Eric T. Harley ,  Yue Ke ,  Henry K. Utomo ,  Yinxiao Yang ,  Zhibin Ren

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/0615 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

摘要： Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

公开(公告)号：US09406569B2

公开(公告)日：2016-08-02

申请号：US14519493

申请日：2014-10-21

申请人： GLOBALFOUNDRIES INC.

发明人： Gregory G. Freeman ,  Kam Leung Lee ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L27/108 ,  H01L29/78 ,  H01L21/84 ,  H01L21/265 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/324 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/3247 ,  H01L21/76243 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/0623 ,  H01L29/66181 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78687 ,  H01L29/78696

摘要： A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

摘要翻译： 绝缘体上半导体（SOI）衬底包括体半导体衬底，形成在本体衬底上的掩埋绝缘体层和形成在掩埋绝缘体层上的有源半导体层。 杂质植入到埋入绝缘体层和有源半导体层的界面附近。 在杂质和有源半导体层的上表面之间形成扩散阻挡层。 扩散阻挡层防止杂质从其中扩散。

公开(公告)号：US10181468B2

公开(公告)日：2019-01-15

申请号：US15338512

申请日：2016-10-31

申请人： GLOBALFOUNDRIES Inc.

发明人： Ziyan Xu ,  Chengwen Pei ,  Xusheng Wu

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

摘要： An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

公开(公告)号：US09972621B1

公开(公告)日：2018-05-15

申请号：US15483344

申请日：2017-04-10

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng Wu ,  Chengwen Pei ,  Ziyan Xu

IPC分类号： H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/16 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L27/0886 ,  H01L21/02236 ,  H01L21/31053 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.

公开(公告)号：US09870942B1

公开(公告)日：2018-01-16

申请号：US15410032

申请日：2017-01-19

申请人： GLOBALFOUNDRIES Inc.

发明人： Xusheng Wu ,  Ziyan Xu ,  Chengwen Pei

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3115 ,  H01L23/528

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/31155 ,  H01L23/5283

摘要： A method includes providing a semiconductor structure having a silicon mandrel layer, a hardmask stack and a dielectric layer. A 1st portion and a 2nd portion of the mandrel layer are doped with a 1st concentration and a 2nd greater concentration of dopant respectively. 1st and 2nd mandrels are patterned into the 1st and 2nd portions of the mandrel layer respectively. The 1st and 2nd mandrels are oxidized in the same thermal oxidation process to form 1st oxidation spacers on sidewalls of the 1st mandrels and 2nd oxidation spacers on sidewalls of the 2nd mandrels. The 2nd oxidation spacers have a thickness that is greater than a thickness of the 1st oxidation spacers. The 1st and 2nd oxidation spacers are utilized to form 1st and 2nd metal lines respectively in the dielectric layer. The 1st and 2nd metal lines have a different thickness.

公开(公告)号：US20170317166A1

公开(公告)日：2017-11-02

申请号：US15142838

申请日：2016-04-29

申请人： GLOBALFOUNDRIES INC.

发明人： Chengwen Pei ,  Hanyi Ding ,  Ping-Chuan Wang ,  Kai D. Feng

IPC分类号： H01L29/06 ,  H01L21/76 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/762

CPC分类号： H01L21/32051 ,  H01L21/3065 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/76229

摘要： Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.

公开(公告)号：US20170316986A1

公开(公告)日：2017-11-02

申请号：US15140025

申请日：2016-04-27

申请人： GLOBALFOUNDRIES INC.

发明人： Chengwen Pei ,  Ping-Chuan Wang ,  Kai D. Feng

IPC分类号： H01L21/84 ,  H01L21/28 ,  H01L21/3065 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

公开(公告)号：US09478600B2

公开(公告)日：2016-10-25

申请号：US14175587

申请日：2014-02-07

申请人： GLOBALFOUNDRIES INC.

发明人： Geng Wang ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L49/02 ,  H01L21/762 ,  H01L21/74 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/743 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/1203 ,  H01L28/91 ,  H01L29/0649 ,  H01L29/66181

摘要： A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided.