Invention Grant
- Patent Title: Fin structure in sublitho dimension for high performance CMOS application
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Application No.: US15483344Application Date: 2017-04-10
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Publication No.: US09972621B1Publication Date: 2018-05-15
- Inventor: Xusheng Wu , Chengwen Pei , Ziyan Xu
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L27/088 ; H01L29/66 ; H01L29/06 ; H01L21/3105 ; H01L21/02 ; H01L29/16 ; H01L29/78 ; H01L21/8234

Abstract:
A method of forming straight and narrow fins in the channel region and the resulting device are provided. Embodiments include forming Si fins separated by STI regions; recessing the STI regions to reveal the Si fins; forming a nitride layer over the STI regions and the Si fins; forming an OPL over the nitride layer between the Si fins; recessing the OPL to expose portions of the nitride layer over the Si fins; removing exposed portions of the nitride layer; removing the OPL; forming an oxide layer over exposed portions of the Si fins; forming a dummy gate over the nitride layer and the oxide layer perpendicular to the Si fins and surrounded by an ILD; removing the dummy gate and the oxide layer forming a cavity; thinning the Si fins in the cavity; and forming a RMG in the cavity.
Information query
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