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    Integrated circuit fabrication with boron etch-stop layer
    2.
    发明授权
    Integrated circuit fabrication with boron etch-stop layer 有权

    公开(公告)号：US10224418B2

    公开(公告)日：2019-03-05

    申请号：US15793419

    申请日：2017-10-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

    IPC: H01L23/48 ,  H01L29/66 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L29/78 ,  H01L29/207 ,  H01L21/311

    Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

    Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming
    5.
    发明授权
    Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming 有权

    公开(公告)号：US10181468B2

    公开(公告)日：2019-01-15

    申请号：US15338512

    申请日：2016-10-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ziyan Xu ,  Chengwen Pei ,  Xusheng Wu

    IPC: H01L29/51 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234

    Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

    METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING NOTCH WITHIN FIN FILLED WITH RARE EARTH OXIDE AND RELATED STRUCTURE
    8.
    发明申请
    METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURES INCLUDING NOTCH WITHIN FIN FILLED WITH RARE EARTH OXIDE AND RELATED STRUCTURE 审中-公开

    公开(公告)号：US20180366562A1

    公开(公告)日：2018-12-20

    申请号：US15627715

    申请日：2017-06-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Xusheng Wu ,  Chengwen Pei ,  Ziyan Xu

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06

    Abstract: The disclosure is directed to methods of forming an integrated circuit structure and a related structure. One method may include: forming a gate structure over a fin, the fin being formed over a substrate and the gate structure defining a channel region beneath the gate structure within the fin; forming a notch within the fin and beneath the channel region by laterally etching the fin on opposing sides of the channel region; forming a rare-earth oxide (REO) within the notch and extending along a top surface of the fin outside of the notch; and forming a source region and a drain region on opposing sides of the channel region and over the REO that is disposed along the top surface of the fin.

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