公开(公告)号：US09240482B2

公开(公告)日：2016-01-19

申请号：US14476897

申请日：2014-09-04

申请人： GLOBALFOUNDRIES INC.

发明人： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L27/108

CPC分类号： H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

摘要： A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

摘要翻译： 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平坦化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。