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    BACK END OF LINE RESISTOR STRUCTURE
    2.
    发明申请
    BACK END OF LINE RESISTOR STRUCTURE 有权

    公开(公告)号：US20250096120A1

    公开(公告)日：2025-03-20

    申请号：US18515521

    申请日：2023-11-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Yu LIAO ,  Chung-Liang Cheng

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

    Gate capping structures in semiconductor devices
    7.
    发明授权
    Gate capping structures in semiconductor devices 有权

    公开(公告)号：US11728413B2

    公开(公告)日：2023-08-15

    申请号：US17244428

    申请日：2021-04-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Liang Cheng

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

    CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/7851

    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

    Metal loss prevention in conductive structures
    10.
    发明授权
    Metal loss prevention in conductive structures 有权

    公开(公告)号：US11631640B2

    公开(公告)日：2023-04-18

    申请号：US17675302

    申请日：2022-02-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

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