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    Clock Circuitry for Memory Applications
    1.
    发明公开
    Clock Circuitry for Memory Applications 审中-公开

    公开(公告)号：US20240290363A1

    公开(公告)日：2024-08-29

    申请号：US18113438

    申请日：2023-02-23

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Sanjay Mangal ,  Hemavathi Chaya ,  Kyung Woo Kim ,  Pratik Ghanshambhai Satasia ,  Edward Martin McCombs

    IPC: G11C7/22 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C7/222 ,  G11C11/418 ,  G11C11/419

    Abstract: Various implementations described herein are related to a device with a first clock generator that provides a first pulse signal based on a clock signal, wherein the first clock generator has a first tracking circuit that provides a first reset signal based on the first pulse signal. The device may include a second clock generator that provides a second pulse signal based on the clock signal, wherein the second clock generator has a second tracking circuit that provides a first control signal based on the second pulse signal. Also, the device may include a third clock generator that provides a third pulse signal based on the first reset signal, wherein the third clock generator has a logic circuit that provides a second control signal based on the third pulse signal.

    Multi-Tier Memory Architecture
    2.
    发明申请
    Multi-Tier Memory Architecture 有权

    公开(公告)号：US20220343970A1

    公开(公告)日：2022-10-27

    申请号：US17238683

    申请日：2021-04-23

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Mudit Bhargava ,  Andy Wangkun Chen

    IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06

    Abstract: Various implementations described herein are directed to a device having a multi-tiered memory structure with a first tier and a second tier arranged vertically in a stacked configuration. The device may have multiple transistors disposed in the multi-tiered memory structure with first transistors disposed in the first tier and second transistors disposed in the second tier. The device may have a single interconnect that vertically couples the first transistors in the first tier to the second transistors in the second tier.

    Methods and circuits of spatial alignment
    4.
    发明授权
    Methods and circuits of spatial alignment 有权

    公开(公告)号：US12223010B2

    公开(公告)日：2025-02-11

    申请号：US17339895

    申请日：2021-06-04

    Applicant: Arm Limited

    Inventor： Supreet Jeloka ,  Mudit Bhargava ,  Saurabh Pijuskumar Sinha ,  Rahul Mathur

    IPC: G06F17/16 ,  G06F9/30

    Abstract: According to one implementation of the present disclosure, a method includes performing a spatial alignment of at least one of first or second data tiers of a circuit; and performing a computation based on the spatial alignment of the at least one of the first and second data tiers. According to another implementation of the present disclosure, a circuit includes: a compute circuitry; and at least first and second data tiers of two or more data tiers positioned at least partially overlapping one another. In an example, each of the at least first and second data tiers is coupled to the compute circuitry. In certain implementations, the positioning of the first and second data tiers at least partially overlapping one another corresponds to a spatial alignment.

    TSV Coupled Integrated Circuits and Methods
    7.
    发明申请
    TSV Coupled Integrated Circuits and Methods 有权

    公开(公告)号：US20220130816A1

    公开(公告)日：2022-04-28

    申请号：US17077532

    申请日：2020-10-22

    Applicant: Arm Limited

    Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

    IPC: H01L27/02 ,  H01L25/065 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00 ,  G06F30/31

    Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

    Circuitry Apportioning of an Integrated Circuit
    10.
    发明申请
    Circuitry Apportioning of an Integrated Circuit 有权

    公开(公告)号：US20220246206A1

    公开(公告)日：2022-08-04

    申请号：US17162532

    申请日：2021-01-29

    Applicant: Arm Limited

    Inventor： Mudit Bhargava ,  Rahul Mathur ,  Andy Wangkun Chen

    IPC: G11C11/419 ,  G11C11/418

    Abstract: According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

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