Invention Publication
- Patent Title: Performance Optimization By Sizing Gates And Source/Drain Contacts Differently For Different Transistors
-
Application No.: US17900639Application Date: 2022-08-31
-
Publication No.: US20240072137A1Publication Date: 2024-02-29
- Inventor: Li-Hui Chen , Chun-Hung Chen , Jhon Jhy Liaw
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L27/02 ; H01L27/11 ; H01L27/12 ; H01L29/78
Abstract:
A first transistor includes a first gate, a first source/drain, and a first source/drain contact disposed over the first source/drain. The first gate has a first dimension measured in a first lateral direction. The first source/drain contact has a second dimension measured in the first lateral direction. A second transistor includes a second gate, a second source/drain, and a second source/drain contact disposed over the second source/drain. The second gate has a third dimension measured in the first lateral direction. The second source/drain contact has a fourth dimension measured in the first lateral direction. A first ratio of the first dimension and the second dimension is different from a second ratio of the third dimension and the fourth dimension.
Information query
IPC分类:
