公开(公告)号：US20160225715A1

公开(公告)日：2016-08-04

申请号：US15022434

申请日：2013-11-20

Applicant: Anthony ST. AMOUR ,  Joseph STEIGERWALD ,  INTEL CORPORATION

Inventor： Anthony St. Amour ,  Joseph Steigerwald

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/53266 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor contact of the present description may be fabricated by forming a via through an interlayer dielectric layer disposed on a microelectronic substrate, wherein the via extends from a first surface of the interlayer dielectric layer to the microelectronic substrate forming a via sidewall and exposing a portion of the microelectronic substrate. A conformal contact material layer may then be formed adjacent the exposed portion of the microelectronic substrate, the at least one via sidewall, and the interlayer dielectric first surface. An etch block plug formed within the via proximate the microelectronic substrate. The contact material layer not protected by the etch block plug may be removed followed by the removal of the etch block plug and the filling the via with a conductive material.

Abstract translation: 本描述的晶体管接触可以通过形成通过设置在微电子衬底上的层间电介质层的通孔来制造，其中通孔从层间电介质层的第一表面延伸到形成通孔侧壁的微电子衬底， 的微电子衬底。 然后可以在微电子衬底，至少一个通孔侧壁和层间电介质第一表面的暴露部分附近形成共形接触材料层。 在靠近微电子衬底的通孔内形成蚀刻块塞。 不被蚀刻块塞子保护的接触材料层可以被去除，随后去除蚀刻块塞和用导电材料填充孔。

公开(公告)号：US11437285B2

公开(公告)日：2022-09-06

申请号：US16881514

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Anthony St. Amour ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L27/092 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/822 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US10707133B2

公开(公告)日：2020-07-07

申请号：US15859411

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Anthony St. Amour ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L29/417 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

公开(公告)号：US11887838B2

公开(公告)日：2024-01-30

申请号：US17867369

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Anthony St. Amour ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L21/8234 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L27/088 ,  H10B10/00

CPC classification number: H01L21/823475 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0886 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7854 ,  H10B10/12

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.