公开(公告)号：US20240243172A1

公开(公告)日：2024-07-18

申请号：US18195150

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejik Baek ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L21/8238 ,  H01L25/07 ,  H01L27/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L25/074 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a three-dimensionally-stacked field-effect transistor (3DSFET) device including a plurality of 3DSFETs on a single substrate, wherein each of the 3DSFET includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.

公开(公告)号：US20230335549A1

公开(公告)日：2023-10-19

申请号：US17866343

申请日：2022-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Jaejik Baek ,  Byounghak Hong ,  Saehan Park ,  Kang-ill Seo

IPC: H01L21/822 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L29/66545 ,  H01L29/6656

Abstract: An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.

公开(公告)号：US20240282855A1

公开(公告)日：2024-08-22

申请号：US18228231

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myunghoon JUNG ,  Panjae Park ,  Jaejik Baek ,  Seungchan Yun ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66666

Abstract: Provided is a semiconductor device including a 3DSFET device which includes: a 1st source/drain region; a 2nd source/drain region, above the 1st source/drain region, having a smaller width than the 1st source/drain region, the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure; a 1st contact plug on the 1st source/drain region; a 2nd contact plug on the 2nd source/drain region; and a 2nd isolation structure, between the 1st contact plug and the 2nd contact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation structure.

公开(公告)号：US20230343824A1

公开(公告)日：2023-10-26

申请号：US17964677

申请日：2022-10-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jaejik Baek ,  Gunho Jo ,  Byounghak Hong ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L25/11 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L25/117 ,  H01L29/78696 ,  H01L21/823412 ,  H01L29/78672

Abstract: Provided is a multi-stack semiconductor device that includes: a substrate; a lower field-effect transistor in which a lower channel structure is surrounded by a lower gate structure including a lower work-function metal layer and a lower gate electrode; and an upper field-effect transistor in which an upper channel structure is surrounded by an upper gate structure including an upper work-function metal layer and an upper gate electrode, wherein each of the lower gate electrode and the upper gate electrode includes a metal or a metal compound, and wherein the lower gate electrode comprises polycrystalline silicon (poly-Si) or poly-Si comprising a dopant, and the upper gate electrode comprises a metal or a metal compound.

公开(公告)号：US20240282670A1

公开(公告)日：2024-08-22

申请号：US18221696

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Wonhyuk Hong ,  Myunghoon Jung ,  Jongjin Lee ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: at least one transistor comprising source/drain regions and 1st gate structure; a contact isolation layer below the 1st gate structure; and a backside contact plug connected to at least one of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure, and isolated from the 1st gate structure by the contact isolation layer.

公开(公告)号：US20230395659A1

公开(公告)日：2023-12-07

申请号：US17934533

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumseok Park ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L25/11 ,  H01L21/8234

CPC classification number: H01L29/0673 ,  H01L29/6656 ,  H01L29/78696 ,  H01L29/0847 ,  H01L25/117 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468

Abstract: Transistor devices are provided. A transistor device includes a transistor stack including first and second transistors. The transistor device includes an insulating spacer that is on a sidewall of a first gate of the first transistor and between a plurality of first semiconductor channel layers of the first transistor. Moreover, the transistor device includes a semiconductor spacer that is on a sidewall of a second gate of the second transistor and between a plurality of second semiconductor channel layers of the second transistor. Related methods of forming transistor devices are also provided.

公开(公告)号：US20230361032A1

公开(公告)日：2023-11-09

申请号：US17969440

申请日：2022-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk HONG ,  Jaemyung Choi ,  Jaejik Baek ,  Janggeun Lee ,  Myunghoon Jung ,  Taesun Kim ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76885 ,  H01L21/76865 ,  H01L23/5226

Abstract: A semiconductor device includes a dielectric layer, a plurality of vias formed in the dielectric layer, an adhesion layer deposited on a top surface of the dielectric layer, and a plurality of metal lines. A first metal line of the plurality of metal lines includes a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed.

公开(公告)号：US20250031444A1

公开(公告)日：2025-01-23

申请号：US18380476

申请日：2023-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a three-dimension (3D) stacked semiconductor device which includes: a 1stsource/drain region connected to a 1st channel structure; and a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure, wherein the 2nd channel structure has a smaller length than the 1st channel structure in a channel-length direction, in which the 2nd source/drain region is connected to a 3rd source/drain region through the 2nd channel structure.

公开(公告)号：US20240371880A1

公开(公告)日：2024-11-07

申请号：US18460110

申请日：2023-09-01

Applicant: Samsung Electronics Co, Ltd.

Inventor： SEUNGCHAN YUN ,  Jaejik Baek ,  KANG-ILL Seo

IPC: H01L27/12 ,  H01L21/84

Abstract: An integrated circuit device may comprise an upper transistor on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor between the substrate and the upper transistor. The lower transistor may comprise a lower channel region, an intergate spacer comprising an insulating material and adjacent to a side surface of the lower channel region, and a gate layer. The intergate spacer may be between the side surface of the lower channel region and the gate layer.

公开(公告)号：US20240079330A1

公开(公告)日：2024-03-07

申请号：US18169905

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Jaejik Baek ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/12 ,  H01L21/823475

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower insulating structure, a transistor on the lower insulating structure, the transistor including a source/drain region, a power rail structure in the lower insulating structure, and a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure. The power contact structure may include a lower portion that is in the power rail structure.