Invention Publication
- Patent Title: LIMITED LATERAL GROWTH OF S/D EPI BY OUTER DIELECTRIC LAYER IN 3-DIMENSIONAL STACKED DEVICE
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Application No.: US17866343Application Date: 2022-07-15
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Publication No.: US20230335549A1Publication Date: 2023-10-19
- Inventor: Inchan Hwang , Jaejik Baek , Byounghak Hong , Saehan Park , Kang-ill Seo
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Main IPC: H01L21/822
- IPC: H01L21/822 ; H01L29/66 ; H01L27/06

Abstract:
An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.
Information query
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