公开(公告)号：US20180151556A1

公开(公告)日：2018-05-31

申请号：US15683050

申请日：2017-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok CHOI ,  Chul Sung KIM ,  Jae Eun LEE

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L23/485 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device includes a substrate, a first recess formed in the substrate, a first source/drain filling the first recess, a vertical metal resistor on the first source/drain, and an insulating liner separating the metal resistor from the first source/drain, with the vertical metal resistor being between two gate electrodes.

公开(公告)号：US20250063763A1

公开(公告)日：2025-02-20

申请号：US18441269

申请日：2024-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won Keun CHUNG ,  Geun Woo KIM ,  Jun Ki PARK ,  Wan Don KIM ,  Hyo Seok CHOI

IPC: H01L29/417 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device may include a backside wiring line in a first backside interlayer insulating film, a fin-type pattern on the backside wiring line, a second backside interlayer insulating film between the fin-type pattern and the first backside interlayer insulating film, a gate electrode on the fin-type pattern, a first source/drain pattern on a side of the gate electrode, and a backside source/drain contact in a backside contact hole defined by the fin-type pattern and the second backside interlayer insulating film. The backside source/drain contact may connect the backside wiring line and the first source/drain pattern. The backside source/drain contact may include an upper pattern and a lower pattern. The upper pattern may be between the lower pattern and the first source/drain pattern, and may fill at least a portion of the first backside contact hole. The upper pattern may have a single conductive film structure.

公开(公告)号：US20240154042A1

公开(公告)日：2024-05-09

申请号：US18353276

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Ki PARK ,  Wan Don KIM ,  Jeong Hyuk YIM ,  Hyo Seok CHOI ,  Sung Hwan KIM

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate including an upper surface and a lower surface that are opposite to each other in a first direction, an active pattern which is on the upper surface of the substrate and extends in a second direction, a gate electrode which is on the active pattern and extends in a third direction, a first source/drain pattern which is connected to the active pattern on the upper surface of the substrate, and includes a lower epitaxial region and an upper epitaxial region, the upper epitaxial region including an epitaxial recess, and the lower epitaxial region being inside the epitaxial recess, a first source/drain contact, which is connected to the first source/drain pattern and extends into the substrate, and a contact silicide layer, which is between the first source/drain contact and the first source/drain pattern and contacts the lower epitaxial region.

公开(公告)号：US20230165000A1

公开(公告)日：2023-05-25

申请号：US17970764

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Seok CHOI ,  Kyoung Sun KIM ,  Hee Jeong SON ,  Min Ju KANG ,  Seong Joon AHN

IPC: H01L27/11582 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  G11C5/06

Abstract: A semiconductor memory device includes a cell substrate including a cell array region and an extended region, gate electrodes stacked on the cell substrate, the gate electrodes including molybdenum, and channel structures in the cell array region, the channel structures penetrating the gate electrodes, wherein at least one of the gate electrodes includes at least one void in a region between the channel structures.

公开(公告)号：US20220199790A1

公开(公告)日：2022-06-23

申请号：US17694759

申请日：2022-03-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok LEE ,  Dae Yong KIM ,  Wan Don Kim ,  Jeong Hyuk YIM ,  Won Keun CHUNG ,  Hyo Seok CHOI ,  Sang Jin HYUN

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.

公开(公告)号：US20250072096A1

公开(公告)日：2025-02-27

申请号：US18606375

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Woong SHIM ,  Seong Heum CHOI ,  Do Sun LEE ,  Hyo Seok CHOI ,  Rak Hwan KIM ,  Chung Hwan SHIN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/768 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method of fabricating a semiconductor device includes: forming an active pattern on a substrate, forming a source/drain pattern on the active pattern, forming a contact hole on the source/drain pattern, forming a contact barrier layer, which has an upper surface of a first height based on a bottom surface of the contact hole, in the contact hole, forming a passivation layer on the contact barrier layer in the contact hole, forming a mask layer on the passivation layer in the contact hole, removing an upper portion of the contact barrier layer so that an upper surface of the contact barrier layer has a second height lower than the first height, removing the passivation layer and the mask layer, and forming a contact filling layer, which covers the upper surface of the contact barrier layer and fills the contact hole, in the contact hole.

公开(公告)号：US20240120279A1

公开(公告)日：2024-04-11

申请号：US18471730

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong Hyuk YIM ,  Wan Don KIM ,  Hyun Bae LEE ,  Hyo Seok CHOI ,  Geun Woo KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/535 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device may include a first film and a second film defining parts of a trench, a plug conductive film, a via, and a wiring in the trench. The trench may include a second sub-trench having a second width below a first sub-trench having a first width. The plug conductive film may extend from a first side of the first film to penetrate a bottom face of the trench. An uppermost face of the plug conducive film may be in the trench. The via may include an insulating liner between the plug conductive film and the first film. The uppermost face of the plug conductive film and at least a part of a side wall of the plug conductive film may be in contact with the wiring. An upper face of the insulating liner may be exposed by a bottom face of the second sub-trench.

公开(公告)号：US20240063276A1

公开(公告)日：2024-02-22

申请号：US18380754

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Bok LEE ,  Dae Yong KIM ,  Wan Don KIM ,  Jeong Hyuk YIM ,  Won Keun CHUNG ,  Hyo Seok CHOI ,  Sang Jin HYUN

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/6681 ,  H01L29/0847 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7851

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction, a gate electrode on the active pattern, the gate electrode extending in a second direction intersecting the first direction and including a first portion and a second portion arranged along the second direction, a first contact plug on the gate electrode, the first contact plug being connected to a top surface of the second portion of the gate electrode, a source/drain region in the active pattern on a sidewall of the gate electrode, and a source/drain contact on the source/drain region, a height of a top surface of the source/drain contact being higher than a top surface of the first portion of the gate electrode and lower than the top surface of the second portion of the gate electrode.