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公开(公告)号：US11869821B2
公开(公告)日：2024-01-09
申请号：US17879272
申请日：2022-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeongkwon Ko , Seunghun Shin , Junyeong Heo
IPC: H01L23/31 , H01L25/065 , H01L23/48 , H01L21/56 , H01L25/00
CPC classification number: H01L23/3128 , H01L21/561 , H01L23/481 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2225/06541
Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.
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公开(公告)号：US10418335B2
公开(公告)日：2019-09-17
申请号：US15850336
申请日：2017-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Rae Cho , Sundae Kim , Hyunggil Baek , Namgyu Baek , Seunghun Shin , Donghoon Won
Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.
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公开(公告)号：US20230065076A1
公开(公告)日：2023-03-02
申请号：US18054295
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeongkwon KO , Seunghun Shin , Junyeong Heo
IPC: H01L23/31 , H01L25/065 , H01L23/00 , H01L23/498 , H01L21/48 , H01L21/56 , H01L21/78
Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.
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公开(公告)号：US20220375808A1
公开(公告)日：2022-11-24
申请号：US17879272
申请日：2022-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeongkwon Ko , Seunghun Shin , Junyeong Heo
IPC: H01L23/31 , H01L25/065 , H01L23/48 , H01L21/56 , H01L25/00
Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.
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公开(公告)号：US20240321667A1
公开(公告)日：2024-09-26
申请号：US18387682
申请日：2023-11-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seunghun Shin , Soyeon Kwon , Unbyoung Kang , Yeongkwon Ko
CPC classification number: H01L23/3185 , H01L21/568 , H01L21/78 , H01L25/0657 , H01L25/18 , H01L25/50 , H10B80/00 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/94 , H01L24/97 , H01L2224/05554 , H01L2224/0557 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05669 , H01L2224/05684 , H01L2224/06131 , H01L2224/06136 , H01L2224/06181 , H01L2224/13014 , H01L2224/14131 , H01L2224/14136 , H01L2224/16145 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81815 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/0665
Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface opposite to the first surface, a second semiconductor chip stacked on the first surface of the first semiconductor chip, and a molding layer contacting the first surface of the first semiconductor chip and a sidewall of the second semiconductor chip. The molding layer includes a first sidewall from a lower end of the first semiconductor chip to a first height in a first direction perpendicular to the first surface of the first semiconductor chip, a second sidewall from the first height to a second height in the first direction, and a flat surface that extends from the first height in a second direction that is parallel with the first surface of the first semiconductor chip.
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公开(公告)号：US10283846B2
公开(公告)日：2019-05-07
申请号：US15375778
申请日：2016-12-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wowjin Choi , Sungkee Kim , Dongryul Shin , Junhyuck Lee , Sooyoung Jang , Moonhyuk Choi , Kwangho Kim , Joonbo Park , Hanjae Bae , Seunghun Shin , Chulhyung Yang , Jiwoo Lee
IPC: H01Q1/24 , H01Q1/48 , H01Q1/50 , H01Q1/38 , H01Q1/44 , H01Q5/00 , H01Q9/00 , H01Q21/28 , H01Q1/52
Abstract: An electronic device is provided including a housing including a first plate, a second plate facing the first plate, and a side member between the first and second plate, a radio frequency (RF) circuit, a processor, a ground member, a first electric path connected between a first port of the RF circuit and a first point of a first conductive portion of the side member, a second electric path connected between a second port of the RF circuit and a first point of a second conductive portion of the side member, a third electric path connected between a second point of the first conductive portion and the ground member, a fourth electric path connected between a second point of the second conductive portion and the ground member, and a fifth electric path connected between one point of the second electric path and one point of the third electric path.
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公开(公告)号：US11424172B2
公开(公告)日：2022-08-23
申请号：US17141290
申请日：2021-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeongkwon Ko , Seunghun Shin , Junyeong Heo
IPC: H01L23/31 , H01L25/065 , H01L23/48 , H01L21/56 , H01L25/00
Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.
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公开(公告)号：US20210375709A1
公开(公告)日：2021-12-02
申请号：US17141290
申请日：2021-01-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeongkwon Ko , Seunghun Shin , Junyeong Heo
IPC: H01L23/31 , H01L25/065 , H01L23/48 , H01L25/00 , H01L21/56
Abstract: A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.
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公开(公告)号：US10916509B2
公开(公告)日：2021-02-09
申请号：US16530993
申请日：2019-08-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yun-Rae Cho , Sundae Kim , Hyunggil Baek , Namgyu Baek , Seunghun Shin , Donghoon Won
Abstract: A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.
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10.发明公开
公开(公告)号：US20240312823A1
公开(公告)日：2024-09-19
申请号：US18371774
申请日：2023-09-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yeongkwon Ko , Seunghun Shin , Jihun Jung , Junyeong Heo
IPC: H01L21/683 , H01L21/67 , H01L21/8258
CPC classification number: H01L21/6836 , H01L21/67092 , H01L21/67132 , H01L21/8258 , H01L2221/68336
Abstract: Provide is a method of splitting a semiconductor chip, the method including performing a back-end-of-line (BEOL) process including forming a plurality of chip areas on a semiconductor substrate, forming a splitting area, which separates the plurality of chip areas, on the semiconductor substrate, and forming a wire on a first surface of the semiconductor substrate, forming a cutout auxiliary layer in the splitting area of the first surface of the semiconductor substrate, and performing mechanical machining by bringing a mechanical machining device into contact with the cutout auxiliary layer, wherein the cutout auxiliary layer is adjacent to the plurality of chip areas.
