公开(公告)号：US11664381B2

公开(公告)日：2023-05-30

申请号：US17210873

申请日：2021-03-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/94 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861

CPC classification number: H01L27/0928 ,  H01L27/0262 ,  H01L27/0266 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/94 ,  H01L27/0811 ,  H01L29/861

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate connected to the second node. A second NMOS transistor is coupled between the first node and the ground, a gate connected to the first node, and has a gate connected to the first node. Sources of the first and second PMOS transistors share a P+ doped region in N-type well region, and the first PMOS transistor is disposed between the second PMOS transistor and the first and second NMOS transistors.

公开(公告)号：US11450735B2

公开(公告)日：2022-09-20

申请号：US16952305

申请日：2020-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Yen Lin ,  Wun-Jie Lin ,  Yu-Ti Su ,  Bo-Ting Chen ,  Jen-Chou Tseng ,  Kuo-Ji Chen ,  Sun-Jay Chang ,  Min-Chang Liang

IPC: H01L29/06 ,  H01L27/02 ,  H01L21/76 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265 ,  H01L21/761 ,  H01L21/8234

Abstract: A method includes implanting a first guard ring around a periphery of core circuitry. The implanting of the first guard ring includes implanting a first component a first distance from the core circuitry on a first side of the core circuitry, and implanting a second component a second distance from the core circuitry on a second side of the core circuitry, wherein the second distance is greater than the first distance. The method further includes implanting a second guard ring around the periphery of the core circuitry. The implanting of the second guard ring includes implanting a third component a third distance from the core circuitry on the first side of the core circuitry, and implanting a fourth component a fourth distance from the core circuitry on the second side of the core circuitry, wherein the third distance is greater than the fourth distance.

公开(公告)号：US20210117605A1

公开(公告)日：2021-04-22

申请号：US17129195

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Mohammed Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US10032764B2

公开(公告)日：2018-07-24

申请号：US15257355

申请日：2016-09-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wun-Jie Lin ,  Yu-Ti Su ,  Li-Wei Chu ,  Bo-Ting Chen

IPC: H01L27/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

公开(公告)号：US20250015073A1

公开(公告)日：2025-01-09

申请号：US18347254

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ken-Hao FAN ,  Yu-Ti Su ,  Sheng-Fu Hsu ,  Hao-Hua Hsu

IPC: H01L27/02

Abstract: A semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel MOSFET that includes an n-drain region, and a vertical NPN BJT having a collector that is the n-drain region and a base that is the p-well region. The p-well region is floating.

公开(公告)号：US12170283B2

公开(公告)日：2024-12-17

申请号：US18300563

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yao Huang ,  Wun-Jie Lin ,  Chia-Wei Hsu ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/08 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861 ,  H01L29/94

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

公开(公告)号：US20240274597A1

公开(公告)日：2024-08-15

申请号：US18320724

申请日：2023-05-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Lin HSU ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/8249 ,  H01L29/08

CPC classification number: H01L27/0292 ,  H01L21/8249 ,  H01L27/0274 ,  H01L29/0847 ,  H01L27/0207

Abstract: A circuit includes a substrate, p-well regions over the substrate and including n- channel metal-oxide semiconductor field-effect transistors, n-well regions over the substrate and including p-channel metal-oxide semiconductor field-effect transistors, drain/source regions of protection metal-oxide semiconductor field-effect transistors, and at least one control circuit. First conductive connections connect selected drain/source regions to the p-well regions and the n-well regions, second conductive connections connect selected n-channel metal-oxide semiconductor field-effect transistors and p-channel metal-oxide semiconductor field-effect transistors to one another, and third conductive connections are configured to connect gates of the protection metal-oxide semiconductor field-effect transistors to the at least one control circuit.

公开(公告)号：US11995390B2

公开(公告)日：2024-05-28

申请号：US18064000

申请日：2022-12-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chi-Yu Lu ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jerry Chang Jui Kao ,  Pin-Dai Sue ,  Jiun-Jia Huang ,  Yu-Ti Su ,  Wei-Hsiang Ma

IPC: G06F30/394 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398

CPC classification number: G06F30/394 ,  G03F1/36 ,  G03F1/70 ,  G06F30/398

Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.

公开(公告)号：US11855452B2

公开(公告)日：2023-12-26

申请号：US18063690

申请日：2022-12-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ken-Hao Fan ,  Yu-Ti Su ,  Tzu-Cheng Kao ,  Ming-Fu Tsai ,  Chia-Lin Hsu

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD power clamp device includes an ESD detection circuit; a controlling circuit coupled with the ESD detection circuit; a field effect transistor (FET) coupled with the controlling circuit, and an impedance element coupled with the FET. The FET includes a drain terminal coupled with a first supply node; a gate terminal coupled with the controlling circuit; a source terminal coupled with a second supply node via the impedance element; and a bulk terminal coupled with second supply node.

公开(公告)号：US09461170B2

公开(公告)日：2016-10-04

申请号：US14259908

申请日：2014-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wun-Jie Lin ,  Yu-Ti Su ,  Li-Wei Chu ,  Bo-Ting Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L27/0266 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823821 ,  H01L27/027 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract translation: 在一些实施例中，场效应晶体管结构包括衬底，鳍结构和栅极结构。 翅片结构形成在衬底上。 鳍结构包括第一沟道区，第一源极或漏极区以及第二源极或漏极区。 第一源极或漏极区域以及第二源极或漏极区域分别形成在第一沟道区域的相对端上。 阱区由与第二源极或漏极区域相同的导电类型形成，连接到第二源极或漏极区域并延伸到衬底。 第一栅极结构围绕翅片结构中的第一沟道区域缠绕。