公开(公告)号：US12223247B2

公开(公告)日：2025-02-11

申请号：US18472280

申请日：2023-09-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kumar Lalgudi ,  Ranjith Kumar ,  Mohammed Rabiul Islam ,  Jianyang Xu

IPC: G06F30/367 ,  G06F30/337 ,  G06F30/373 ,  G06F30/392 ,  G06F30/398 ,  G06F119/06 ,  G06F119/12

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

公开(公告)号：US20220302089A1

公开(公告)日：2022-09-22

申请号：US17559718

申请日：2021-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Stefan Rusu ,  Mohammed Rabiul Islam ,  Eric Soenen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

公开(公告)号：US20230237237A1

公开(公告)日：2023-07-27

申请号：US18190309

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Mohammed Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

CPC classification number: G06F30/392 ,  H01L27/0207 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F2117/02

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20240347513A1

公开(公告)日：2024-10-17

申请号：US18752388

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Stefan Rusu ,  Mohammed Rabiul Islam ,  Eric Soenen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

公开(公告)号：US12046580B2

公开(公告)日：2024-07-23

申请号：US17559718

申请日：2021-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Stefan Rusu ,  Mohammed Rabiul Islam ,  Eric Soenen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A three-dimensional integrated circuit (3D IC) package is provided. The 3D IC package includes: a cache die including a low-dropout (LDO) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.

公开(公告)号：US11816412B2

公开(公告)日：2023-11-14

申请号：US17232525

申请日：2021-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kumar Lalgudi ,  Ranjith Kumar ,  Mohammed Rabiul Islam ,  Jianyang Xu

IPC: G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/398 ,  G06F30/337 ,  G06F119/12 ,  G06F119/06

CPC classification number: G06F30/367 ,  G06F30/373 ,  G06F30/392 ,  G06F30/337 ,  G06F30/398 ,  G06F2119/06 ,  G06F2119/12

Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.

公开(公告)号：US20210117605A1

公开(公告)日：2021-04-22

申请号：US17129195

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Mohammed Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.