公开(公告)号：US20210117605A1

公开(公告)日：2021-04-22

申请号：US17129195

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Mohammed Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20230237237A1

公开(公告)日：2023-07-27

申请号：US18190309

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Mohammed Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398

CPC classification number: G06F30/392 ,  H01L27/0207 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F2117/02

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US11615227B2

公开(公告)日：2023-03-28

申请号：US17129195

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/30 ,  G06F30/392 ,  H01L27/02 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F117/02

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20240386180A1

公开(公告)日：2024-11-21

申请号：US18787493

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F30/392 ,  G01R31/50 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F117/02 ,  H01L27/02

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

公开(公告)号：US20200019666A1

公开(公告)日：2020-01-16

申请号：US16263841

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chia Lai ,  Kuo-Ji Chen ,  Wen-Hao Chen ,  Wun-Jie Lin ,  Yu-Ti Su ,  Rabiul Islam ,  Shu-Yi Ying ,  Stefan Rusu ,  Kuan-Te Li ,  David Barry Scott

IPC: G06F17/50 ,  H01L27/02 ,  G01R31/02

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.