公开(公告)号：US12125850B2

公开(公告)日：2024-10-22

申请号：US17234256

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC分类号： H01L27/088 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78 ,  H10B12/00 ,  H01L27/092

CPC分类号： H01L27/0886 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/785 ,  H10B12/31 ,  H10B12/36 ,  H01L27/0924 ,  H10B12/34 ,  H10B12/37

摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US11916077B2

公开(公告)日：2024-02-27

申请号：US17328534

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou ,  Wei-An Lai

IPC分类号： H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L27/11807 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0924 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11888

摘要： The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20230369047A1

公开(公告)日：2023-11-16

申请号：US18361878

申请日：2023-07-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Tien Shen ,  Ya-Wen Yeh ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Wei-Hao Wu ,  Li-Te Lin ,  Ru-Gun Liu ,  Kuei-Shun Chen

IPC分类号： H01L21/027 ,  G03F7/09 ,  H01L21/311 ,  H01L21/033 ,  G03F7/20 ,  H01L21/306 ,  G03F7/11

CPC分类号： H01L21/0273 ,  G03F7/09 ,  H01L21/0337 ,  H01L21/311 ,  G03F7/11 ,  G03F7/20 ,  H01L21/0274 ,  H01L21/306

摘要： The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process, forming a resist layer over the hard mask layer, patterning the resist layer to form a plurality of openings in the resist layer, each of the openings free of concave corners, performing an opening expanding process to enlarge at least one of the openings in the resist layer, transferring the openings in the resist layer to the hard mask layer, and performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.

公开(公告)号：US20230367234A1

公开(公告)日：2023-11-16

申请号：US18360618

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Jie Lee ,  Shih-Chun Huang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Yung-Sung Yen ,  Ru-Gun Liu

IPC分类号： G03F9/00

CPC分类号： G03F9/7026 ,  G03F7/2004

摘要： A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.

公开(公告)号：US11586115B2

公开(公告)日：2023-02-21

申请号：US17411571

申请日：2021-08-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Ming Chang ,  Chiu-Hsiang Chen ,  Ru-Gun Liu

IPC分类号： G03F7/20

摘要： A method of operating a semiconductor apparatus includes generating an electric field in peripheral areas of a first covering structure and a second covering structure; causing a photomask to move to a position between the first and second covering structures such that the photomask at least partially vertically overlaps the first and second covering structures and such that particles attached to the photomask are attracted to the first and second covering structures by the electric field; and irradiating the photomask with light through light transmission regions of the first and second covering structures.

公开(公告)号：US20220367240A1

公开(公告)日：2022-11-17

申请号：US17869142

申请日：2022-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L29/66 ,  H01L23/535

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US11424154B2

公开(公告)日：2022-08-23

申请号：US17116443

申请日：2020-12-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L29/66 ,  H01L23/535 ,  H01L21/762 ,  H01L21/3115 ,  H01L29/78 ,  H01L21/311 ,  H01L21/308 ,  H01L27/11

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

公开(公告)号：US11353324B2

公开(公告)日：2022-06-07

申请号：US16721360

申请日：2019-12-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chui-Jung Chiu ,  Jen-Chieh Lo ,  Ying-Chou Cheng ,  Ru-Gun Liu

IPC分类号： G01B15/04 ,  G01B15/00 ,  H01J37/28

摘要： A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using the measurement tool, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

公开(公告)号：US11239078B2

公开(公告)日：2022-02-01

申请号：US16921032

申请日：2020-07-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC分类号： H01L21/302 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

摘要： A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US11204897B2

公开(公告)日：2021-12-21

申请号：US16669320

申请日：2019-10-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Fu An Tien ,  Changsheng Ying ,  Hsu-Ting Huang ,  Ru-Gun Liu

IPC分类号： G06F16/174 ,  G06F16/16 ,  G06F30/392 ,  G06F30/34 ,  G06F30/36 ,  G06F30/39

摘要： A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction. Multiple result files each in a compressed format are obtained from the distributed computing system and the result files are combined to obtain a single result file without decompressing and re-compressing the results from the distributed computing system.