公开(公告)号：US10930595B2

公开(公告)日：2021-02-23

申请号：US15938258

申请日：2018-03-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Wayne Lai

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118 ,  H01L29/78

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US10784168B2

公开(公告)日：2020-09-22

申请号：US16154035

申请日：2018-10-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC分类号： H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

摘要： The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.

公开(公告)号：US20190165178A1

公开(公告)日：2019-05-30

申请号：US16176074

申请日：2018-10-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang CHEN ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US11688691B2

公开(公告)日：2023-06-27

申请号：US17164449

申请日：2021-02-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Wayne Lai

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L27/02 ,  H01L27/088 ,  H01L27/118 ,  H01L29/78

CPC分类号： H01L23/535 ,  H01L21/76895 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/785 ,  H01L2027/11875 ,  H01L2027/11881

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US11532751B2

公开(公告)日：2022-12-20

申请号：US17068444

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/74 ,  H01L23/538 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/535

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20210280607A1

公开(公告)日：2021-09-09

申请号：US17328534

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang CHEN ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou ,  Wei-An Lai

IPC分类号： H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/02

摘要： The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US11018157B2

公开(公告)日：2021-05-25

申请号：US16022821

申请日：2018-06-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Cheng-Chi Chuang ,  Chih-Ming Lai ,  Chia-Tien Wu ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Ru-Gun Liu ,  Wei-Cheng Lin ,  Lei-Chun Chou ,  Wei-An Lai

IPC分类号： H01L27/118 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532

摘要： The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

公开(公告)号：US20210028311A1

公开(公告)日：2021-01-28

申请号：US17068444

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20190096809A1

公开(公告)日：2019-03-28

申请号：US15938258

申请日：2018-03-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Cheng Lin ,  Cheng-Chi Chuang ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Wayne Lai

IPC分类号： H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768

摘要： The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.

公开(公告)号：US20190043759A1

公开(公告)日：2019-02-07

申请号：US16154035

申请日：2018-10-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC分类号： H01L21/8234 ,  H01L27/088

摘要： The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.