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公开(公告)号：US20240282671A1
公开(公告)日：2024-08-22
申请号：US18327998
申请日：2023-06-02
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Kuan Yu Chen , Chun-Yen Lin , Hsin Yang Hung , Ching-Yu Huang , Wei-Cheng Lin , Jiann-Tyng Tzeng , Ting-Yun Wu , Wei-De Ho , Szuya Liao
IPC: H01L23/48 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/66
CPC classification number: H01L23/481 , H01L21/823814 , H01L21/823871 , H01L27/092 , H01L29/41733 , H01L29/66545
Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.
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公开(公告)号：US11973117B2
公开(公告)日：2024-04-30
申请号：US17392320
申请日：2021-08-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsien Huang , Chang-Ting Chung , Wei-Cheng Lin , Wei-Jung Lin , Chih-Wei Chang
IPC: H01L29/40 , H01L21/02 , H01L21/285 , H01L21/311 , H01L21/768 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/78 , H01L21/3065 , H01L21/321
CPC classification number: H01L29/401 , H01L21/02063 , H01L21/02164 , H01L21/02238 , H01L21/28568 , H01L21/31116 , H01L21/76802 , H01L21/76826 , H01L21/76879 , H01L29/41791 , H01L29/66795 , H01L21/02532 , H01L21/02636 , H01L21/3065 , H01L21/3212 , H01L21/7684 , H01L29/0847 , H01L29/66545 , H01L29/7848
Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
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公开(公告)号：US11916077B2
公开(公告)日：2024-02-27
申请号：US17328534
申请日：2021-05-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Liang Chen , Cheng-Chi Chuang , Chih-Ming Lai , Chia-Tien Wu , Charles Chew-Yuen Young , Hui-Ting Yang , Jiann-Tyng Tzeng , Ru-Gun Liu , Wei-Cheng Lin , Lei-Chun Chou , Wei-An Lai
IPC: H01L27/118 , H01L27/092 , H01L23/522 , H01L21/8238 , H01L27/02 , H01L23/528 , H01L23/532
CPC classification number: H01L27/11807 , H01L21/823821 , H01L21/823871 , H01L23/5226 , H01L27/0207 , H01L27/0924 , H01L23/5286 , H01L23/53209 , H01L23/53228 , H01L23/53242 , H01L2027/11875 , H01L2027/11881 , H01L2027/11888
Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
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公开(公告)号：US20230387221A1
公开(公告)日：2023-11-30
申请号：US18447053
申请日：2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsien Huang , Chang-Ting Chung , Wei-Cheng Lin , Wei-Jung Lin , Chih-Wei Chang
IPC: H01L29/40 , H01L21/02 , H01L21/768 , H01L21/311 , H01L21/285 , H01L29/66 , H01L29/417
CPC classification number: H01L29/401 , H01L21/02238 , H01L21/76879 , H01L21/02164 , H01L21/31116 , H01L21/3212 , H01L21/28568 , H01L29/66795 , H01L21/02063 , H01L29/41791 , H01L21/76802 , H01L21/76826
Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
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公开(公告)号：US20210367042A1
公开(公告)日：2021-11-25
申请号：US17392320
申请日：2021-08-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Hsien Huang , Chang-Ting Chung , Wei-Cheng Lin , Wei-Jung Lin , Chih-Wei Chang
IPC: H01L29/40 , H01L21/02 , H01L21/768 , H01L21/311 , H01L21/285 , H01L29/66 , H01L29/417
Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.
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公开(公告)号：US11043426B2
公开(公告)日：2021-06-22
申请号：US16578357
申请日：2019-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Ting Yang , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Meng-Hung Shen , Ru-Gun Liu , Wei-Cheng Lin
IPC: H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/78 , H01L29/49 , H01L29/66
Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.
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公开(公告)号：US20200020588A1
公开(公告)日：2020-01-16
申请号：US16578357
申请日：2019-09-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Ting Yang , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Meng-Hung Shen , Ru-Gun Liu , Wei-Cheng Lin
IPC: H01L21/8234 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78
Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a plurality of gate structures over a substrate, and forming a plurality of source and drain regions along opposing sides of the plurality of gate structures. A plurality of middle-of-the-line (MOL) structures are formed at locations laterally interleaved between the plurality of gate structures. The plurality of MOL structures are redefined by getting rid of a part but not all of one or more of the plurality of MOL structures. Redefining the plurality of MOL structures results in a plurality of MOL active structures arranged over the plurality of source and drain regions at an irregular pitch.
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公开(公告)号：US10522542B1
公开(公告)日：2019-12-31
申请号：US16021847
申请日：2018-06-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Wei Peng , Hui-Zhong Zhuang , Jiann-Tyng Tzeng , Li-Chun Tien , Pin-Dai Sue , Wei-Cheng Lin
IPC: H01L21/70 , H01L27/092 , H03K17/687
Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.
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公开(公告)号：US10096522B2
公开(公告)日：2018-10-09
申请号：US15148274
申请日：2016-05-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Ting Yang , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Meng-Hung Shen , Ru-Gun Liu , Wei-Cheng Lin
IPC: H01L21/82 , H01L21/8234 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/49
Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.
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公开(公告)号：US20170323832A1
公开(公告)日：2017-11-09
申请号：US15148274
申请日：2016-05-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hui-Ting Yang , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Meng-Hung Shen , Ru-Gun Liu , Wei-Cheng Lin
IPC: H01L21/8234 , H01L29/66 , H01L29/423 , H01L27/092 , H01L29/78 , H01L29/49
CPC classification number: H01L21/823437 , H01L21/823431 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L29/4238 , H01L29/4916 , H01L29/6653 , H01L29/66545 , H01L29/785
Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.
